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| author | Subrata Banik <subratabanik@google.com> | 2022-11-24 21:51:42 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-12-02 07:51:52 +0000 |
| commit | 17a3da8b9946dde434c7f1ab8cf14cbb1597373b (patch) | |
| tree | b6928437a9f66ae43e68167f65876af102d52783 /src/soc/intel/common | |
| parent | 5214c4091f2c747616873f37c086dbd57387f6a0 (diff) | |
| download | coreboot-17a3da8b9946dde434c7f1ab8cf14cbb1597373b.tar.gz coreboot-17a3da8b9946dde434c7f1ab8cf14cbb1597373b.tar.bz2 coreboot-17a3da8b9946dde434c7f1ab8cf14cbb1597373b.zip | |
soc/intel/cmn/cse: API to perform essential CSE operations post EOP
This patch creates an API that can perform essential CSE operation
after sending the late EOP command to the CSE and prior booting to OS.
Lists of operation are
- Perform global reset lock
- Put HECI1 to D0i3 and disable the HECI1 if the user selects
- Set D0I3 for all HECI devices.
BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 16 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 6 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 9b8db54efd61..8f32c7ce61d1 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1256,6 +1256,22 @@ static void cse_final_end_of_firmware(void) } /* + * This function to perform essential post EOP cse related operations + * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config + */ +void cse_late_finalize(void) +{ + if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) + return; + + if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) + cse_final_ready_to_boot(); + + if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) + cse_final_end_of_firmware(); +} + +/* * `cse_final` function is native implementation of equivalent events performed by * each FSP NotifyPhase() API invocations. */ diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index cceee4f8aca3..bccdc4ead403 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -542,6 +542,12 @@ void cse_control_global_reset_lock(void); void cse_send_end_of_post(void); /* + * This function to perform essential post EOP cse related operations + * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config + */ +void cse_late_finalize(void); + +/* * SoC override API to make heci1 disable using PCR. * * Allow SoC to implement heci1 disable override due to PSF registers being |