diff options
| author | Aseda Aboagye <aaboagye@google.com> | 2021-06-15 22:46:15 -0700 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2021-06-18 21:05:11 +0000 |
| commit | 193ee64d52a707809982231cd857329fe17f9f99 (patch) | |
| tree | c9e412e4a5d7f7ab61710689af359371e10949b0 /src/soc/intel/common | |
| parent | bda86bd4974ceb279392711617eec48f37306717 (diff) | |
| download | coreboot-193ee64d52a707809982231cd857329fe17f9f99.tar.gz coreboot-193ee64d52a707809982231cd857329fe17f9f99.tar.bz2 coreboot-193ee64d52a707809982231cd857329fe17f9f99.zip | |
soc/intel/common: Fix bugs for GPIO_LOCK_UNLOCK
Per the Intel External Design Specification (doc #618876), the opcode
for GPIO_LOCK_UNLOCK is 0x13. This commit fixes a bug where the opcode
was defined as 13 decimal instead of hexadecimal. Additionally, it
fixes another issue where the `pcr_execute_sideband_msg()` function
doesn't actually write the data when this opcode is selected.
BUG=b:191189275
BRANCH=None
TEST=With additional code that uses this opcode, verify that the lock
functionality works by locking a pad in firmware and attempting to
modify the configuration of the pad from the OS.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Ie14fff595474cdfd647c2b36f1eeb5e018f67375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55556
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pcr.h | 14 | ||||
| -rw-r--r-- | src/soc/intel/common/block/pcr/pcr.c | 1 |
2 files changed, 8 insertions, 7 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pcr.h b/src/soc/intel/common/block/include/intelblocks/pcr.h index dd02f0fe5224..e4a9fb82f851 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcr.h +++ b/src/soc/intel/common/block/include/intelblocks/pcr.h @@ -27,13 +27,13 @@ void pcr_or8(uint8_t pid, uint16_t offset, uint8_t ordata); /* SBI command */ enum { - MEM_READ = 0, - MEM_WRITE = 1, - PCI_CONFIG_READ = 4, - PCI_CONFIG_WRITE = 5, - PCR_READ = 6, - PCR_WRITE = 7, - GPIO_LOCK_UNLOCK = 13, + MEM_READ = 0x00, + MEM_WRITE = 0x01, + PCI_CONFIG_READ = 0x04, + PCI_CONFIG_WRITE = 0x05, + PCR_READ = 0x06, + PCR_WRITE = 0x07, + GPIO_LOCK_UNLOCK = 0x13, }; struct pcr_sbi_msg { diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index 96b93ad37a66..989805d1258e 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -330,6 +330,7 @@ int pcr_execute_sideband_msg(struct pcr_sbi_msg *msg, uint32_t *data, case MEM_WRITE: case PCI_CONFIG_WRITE: case PCR_WRITE: + case GPIO_LOCK_UNLOCK: /* * 6. Write P2SB PCI offset D4h[31:0] with the * intended data accordingly |