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| author | Subrata Banik <subratabanik@google.com> | 2022-12-13 14:10:48 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-12-15 08:11:30 +0000 |
| commit | 5dfec718290609dc0fd0331070ad703107e0b7e7 (patch) | |
| tree | f0190e070476d72bef9ff7500feab5cd34ff2004 /src/soc/intel/common | |
| parent | 0f15030700ae0c9a4102b3f3d6551a1a7e502c14 (diff) | |
| download | coreboot-5dfec718290609dc0fd0331070ad703107e0b7e7.tar.gz coreboot-5dfec718290609dc0fd0331070ad703107e0b7e7.tar.bz2 coreboot-5dfec718290609dc0fd0331070ad703107e0b7e7.zip | |
soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions
As per PCI Express Base Specification 5.0 section 5.4.1.3 ASPM
Configuration
+-----------------------+-------------------------------+
| Field Description | ASPM Support |
+-----------------------+-------------------------------+
| 00b | No ASPM support |
+-----------------------+-------------------------------+
| 01b | L0s Supported |
+-----------------------+-------------------------------+
| 10b | L1 Supported |
+-----------------------+-------------------------------+
| 11b | L0s and L1 Supported |
+-----------------------+-------------------------------+
100b aka 0x4 is added by FSP to allow auto configuration (to avoid
conflicting with the PCI specification defined values).
Additionally, changed enum definition which is now meeting the FSP expectations better.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8c9055f721e144f2ff5055e5f99ea641efc4d268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70719
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pcie_rp.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 9832feb83fe8..a4e350055efe 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -46,7 +46,6 @@ enum L1_substates_control { /* This enum is for passing into an FSP UPD, typically ASPM */ enum ASPM_control { - ASPM_DEFAULT, ASPM_DISABLE, ASPM_L0S, ASPM_L1, |