soc/intel/cmn: Support for ME spec versions for SoCs at common code

This patch includes ME specification datastructures for various ME
versions. Including the ME specification in common code will help
current and future SoC platforms to select the correct version based on
the applicable configuration. It might be also beneficial if two
different SoC platforms would like to use the same ME specification and
not necessarily share the same SoC directory.

BUG=b:260309647
Test=Build verified for brya and rex.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I83df41d7180d2df419849a0c01c728ff0fe75378
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73129
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 416 insertions, 1 deletions

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 2928a4e6c607..25a04ed30459 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -11,6 +11,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <intelblocks/cse.h>
+#include <intelblocks/me.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/post_codes.h>
 #include <option.h>
@@ -19,7 +20,6 @@
 #include <soc/intel/common/reset.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
-#include <soc/me.h>
 #include <string.h>
 #include <timer.h>
 #include <types.h>
diff --git a/src/soc/intel/common/block/include/intelblocks/me.h b/src/soc/intel/common/block/include/intelblocks/me.h
new file mode 100644
index 000000000000..c55d147f13a4
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/me.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_INTEL_COMMON_ME_SPEC_H_
+#define _SOC_INTEL_COMMON_ME_SPEC_H_
+
+#include <stdint.h>
+#if CONFIG(SOC_INTEL_CSE_HAVE_SPEC_SUPPORT)
+
+#if CONFIG_ME_SPEC == 12
+#include "me_12.h"
+#elif CONFIG_ME_SPEC == 13
+#include "me_13.h"
+#elif CONFIG_ME_SPEC == 15
+#include "me_15.h"
+#elif CONFIG_ME_SPEC == 16
+#include "me_16.h"
+#elif CONFIG_ME_SPEC == 18
+#include "me_18.h"
+#endif
+
+#else
+#include <soc/me.h>
+#endif /* SOC_INTEL_CSE_HAVE_SPEC_SUPPORT */
+
+#endif /* _SOC_INTEL_COMMON_ME_SPEC_H_ */
diff --git a/src/soc/intel/common/block/include/intelblocks/me_12.h b/src/soc/intel/common/block/include/intelblocks/me_12.h
new file mode 100644
index 000000000000..9e9a3c183494
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/me_12.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_INTEL_COMMON_ME_SPEC_12_H_
+#define _SOC_INTEL_COMMON_ME_SPEC_12_H_
+
+/* ME Host Firmware Status register 1 */
+union me_hfsts1 {
+	uint32_t data;
+	struct {
+		uint32_t working_state		: 4;
+		uint32_t mfg_mode		: 1;
+		uint32_t fpt_bad		: 1;
+		uint32_t operation_state	: 3;
+		uint32_t fw_init_complete	: 1;
+		uint32_t ft_bup_ld_flr		: 1;
+		uint32_t update_in_progress	: 1;
+		uint32_t error_code		: 4;
+		uint32_t operation_mode		: 4;
+		uint32_t reserved_0		: 4;
+		uint32_t boot_options_present	: 1;
+		uint32_t reserved_1		: 6;
+		uint32_t d0i3_support_valid	: 1;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 2 */
+union me_hfsts2 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 4;
+		uint32_t cpu_replaced		: 1;
+		uint32_t reserved_1		: 3;
+		uint32_t cpu_replaced_valid	: 1;
+		uint32_t low_power_state	: 1;
+		uint32_t reserved_2		: 22;
+	} __packed fields;
+};
+
+/* ME Host Firmware Status Register 3 */
+union me_hfsts3 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 4;
+		uint32_t fw_sku			: 3;
+		uint32_t reserved_1		: 25;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 4 */
+union me_hfsts4 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 5 */
+union me_hfsts5 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 6 */
+union me_hfsts6 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 1;
+		uint32_t cpu_debug_disable	: 1;
+		uint32_t reserved_1		: 29;
+		uint32_t txt_support		: 1;
+	} __packed fields;
+};
+
+#endif /* _SOC_INTEL_COMMON_ME_SPEC_12_H_ */
diff --git a/src/soc/intel/common/block/include/intelblocks/me_13.h b/src/soc/intel/common/block/include/intelblocks/me_13.h
new file mode 100644
index 000000000000..912930d6adc5
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/me_13.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_INTEL_COMMON_ME_SPEC_13_H_
+#define _SOC_INTEL_COMMON_ME_SPEC_13_H_
+
+/* ME Host Firmware Status register 1 */
+union me_hfsts1 {
+	uint32_t data;
+	struct {
+		uint32_t working_state		: 4;
+		uint32_t mfg_mode		: 1;
+		uint32_t fpt_bad		: 1;
+		uint32_t operation_state	: 3;
+		uint32_t fw_init_complete	: 1;
+		uint32_t ft_bup_ld_flr		: 1;
+		uint32_t update_in_progress	: 1;
+		uint32_t error_code		: 4;
+		uint32_t operation_mode		: 4;
+		uint32_t reserved_0		: 4;
+		uint32_t boot_options_present	: 1;
+		uint32_t reserved_1		: 6;
+		uint32_t d0i3_support_valid	: 1;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 2 */
+union me_hfsts2 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 4;
+		uint32_t cpu_replaced		: 1;
+		uint32_t reserved_1		: 3;
+		uint32_t cpu_replaced_valid	: 1;
+		uint32_t low_power_state	: 1;
+		uint32_t reserved_2		: 22;
+	} __packed fields;
+};
+
+/* ME Host Firmware Status Register 3 */
+union me_hfsts3 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 4;
+		uint32_t fw_sku			: 3;
+		uint32_t reserved_1		: 25;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 4 */
+union me_hfsts4 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 5 */
+union me_hfsts5 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 6 */
+union me_hfsts6 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 1;
+		uint32_t cpu_debug_disable	: 1;
+		uint32_t reserved_1		: 29;
+		uint32_t txt_support		: 1;
+	} __packed fields;
+};
+#endif /* _SOC_INTEL_COMMON_ME_SPEC_13_H_ */
diff --git a/src/soc/intel/common/block/include/intelblocks/me_15.h b/src/soc/intel/common/block/include/intelblocks/me_15.h
new file mode 100644
index 000000000000..60fbbae5205b
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/me_15.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_INTEL_COMMON_ME_SPEC_15_H_
+#define _SOC_INTEL_COMMON_ME_SPEC_15_H_
+
+/* ME Host Firmware Status register 1 */
+union me_hfsts1 {
+	uint32_t data;
+	struct {
+		uint32_t working_state		: 4;
+		uint32_t mfg_mode		: 1;
+		uint32_t fpt_bad		: 1;
+		uint32_t operation_state	: 3;
+		uint32_t fw_init_complete	: 1;
+		uint32_t ft_bup_ld_flr		: 1;
+		uint32_t update_in_progress	: 1;
+		uint32_t error_code		: 4;
+		uint32_t operation_mode		: 4;
+		uint32_t reserved_0		: 4;
+		uint32_t boot_options_present	: 1;
+		uint32_t invoke_enhance_dbg_mode: 1;
+		uint32_t reserved_1		: 5;
+		uint32_t d0i3_support_valid	: 1;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 2 */
+union me_hfsts2 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 4;
+		uint32_t cpu_replaced		: 1;
+		uint32_t reserved_1		: 3;
+		uint32_t cpu_replaced_valid	: 1;
+		uint32_t low_power_state	: 1;
+		uint32_t reserved_2		: 22;
+	} __packed fields;
+};
+
+/* ME Host Firmware Status Register 3 */
+union me_hfsts3 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 4;
+		uint32_t fw_sku			: 3;
+		uint32_t reserved_1		: 25;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 4 */
+union me_hfsts4 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 5 */
+union me_hfsts5 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 6 */
+union me_hfsts6 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 1;
+		uint32_t cpu_debug_disable	: 1;
+		uint32_t reserved_1		: 28;
+		uint32_t fpf_soc_lock		: 1;
+		uint32_t txt_support		: 1;
+	} __packed fields;
+};
+#endif /* _SOC_INTEL_COMMON_ME_SPEC_15_H_ */
diff --git a/src/soc/intel/common/block/include/intelblocks/me_16.h b/src/soc/intel/common/block/include/intelblocks/me_16.h
new file mode 100644
index 000000000000..ef3dbd1b4c07
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/me_16.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_INTEL_COMMON_ME_SPEC_16_H_
+#define _SOC_INTEL_COMMON_ME_SPEC_16_H_
+
+/* ME Host Firmware Status register 1 */
+union me_hfsts1 {
+	uint32_t data;
+	struct {
+		uint32_t working_state		: 4;
+		uint32_t mfg_mode		: 1;
+		uint32_t fpt_bad		: 1;
+		uint32_t operation_state	: 3;
+		uint32_t fw_init_complete	: 1;
+		uint32_t ft_bup_ld_flr		: 1;
+		uint32_t update_in_progress	: 1;
+		uint32_t error_code		: 4;
+		uint32_t operation_mode		: 4;
+		uint32_t reserved_0		: 4;
+		uint32_t boot_options_present	: 1;
+		uint32_t invoke_enhance_dbg_mode: 1;
+		uint32_t reserved_1		: 5;
+		uint32_t d0i3_support_valid	: 1;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 2 */
+union me_hfsts2 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 4;
+		uint32_t cpu_replaced		: 1;
+		uint32_t reserved_1		: 3;
+		uint32_t cpu_replaced_valid	: 1;
+		uint32_t low_power_state	: 1;
+		uint32_t reserved_2		: 22;
+	} __packed fields;
+};
+
+/* ME Host Firmware Status Register 3 */
+union me_hfsts3 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 4;
+		uint32_t fw_sku			: 3;
+		uint32_t reserved_1		: 25;
+	} __packed fields;
+};
+
+
+/* Host Firmware Status Register 4 */
+union me_hfsts4 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 5 */
+union me_hfsts5 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 6 */
+union me_hfsts6 {
+	u32 data;
+	struct {
+		uint32_t reserved_0		: 1;
+		uint32_t cpu_debug_disable	: 1;
+		uint32_t reserved_1		: 19;
+		uint32_t manuf_lock		: 1;
+		uint32_t reserved_2		: 8;
+		uint32_t fpf_soc_lock		: 1;
+		uint32_t txt_support		: 1;
+	} __packed fields;
+};
+
+#endif /* _SOC_INTEL_COMMON_ME_SPEC_16_H_ */
diff --git a/src/soc/intel/common/block/include/intelblocks/me_18.h b/src/soc/intel/common/block/include/intelblocks/me_18.h
new file mode 100644
index 000000000000..b226ebc50190
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/me_18.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_INTEL_COMMON_ME_SPEC_18_H_
+#define _SOC_INTEL_COMMON_ME_SPEC_18_H_
+
+/* ME Host Firmware Status register 1 */
+union me_hfsts1 {
+	uint32_t data;
+	struct {
+		uint32_t working_state		: 4;
+		uint32_t mfg_mode		: 1;
+		uint32_t fpt_bad		: 1;
+		uint32_t operation_state	: 3;
+		uint32_t fw_init_complete	: 1;
+		uint32_t ft_bup_ld_flr		: 1;
+		uint32_t update_in_progress	: 1;
+		uint32_t error_code		: 4;
+		uint32_t operation_mode		: 4;
+		uint32_t reserved_0		: 4;
+		uint32_t boot_options_present	: 1;
+		uint32_t invoke_enhance_dbg_mode: 1;
+		uint32_t reserved_1		: 5;
+		uint32_t d0i3_support_valid	: 1;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 2 */
+union me_hfsts2 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 4;
+		uint32_t cpu_replaced		: 1;
+		uint32_t reserved_1		: 3;
+		uint32_t cpu_replaced_valid	: 1;
+		uint32_t low_power_state	: 1;
+		uint32_t reserved_2		: 22;
+	} __packed fields;
+};
+
+/* ME Host Firmware Status Register 3 */
+union me_hfsts3 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 4;
+		uint32_t fw_sku			: 3;
+		uint32_t reserved_1		: 25;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 4 */
+union me_hfsts4 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 5 */
+union me_hfsts5 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 17;
+		uint32_t txt_support		: 1;
+		uint32_t reserved_1		: 3;
+		uint32_t cpu_debug_disabled	: 1;
+		uint32_t reserved_2		: 10;
+	} __packed fields;
+};
+
+/* Host Firmware Status Register 6 */
+union me_hfsts6 {
+	uint32_t data;
+	struct {
+		uint32_t reserved_0		: 21;
+		uint32_t manuf_lock		: 1;
+		uint32_t reserved_1		: 8;
+		uint32_t fpf_soc_lock		: 1;
+		uint32_t reserved_2		: 1;
+	} __packed fields;
+};
+#endif /* _SOC_INTEL_COMMON_ME_SPEC_18_H_ */