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| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-25 10:09:35 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-28 04:16:48 +0000 |
| commit | f585c6eeeafb575cc64452d8519a172ffb4ffc8b (patch) | |
| tree | 352be415388c8f1baa98b3f5641f2f6f05f19260 /src/soc/intel/common | |
| parent | c44ffc30846fdfa7cf814316d24dfecd2c22b0ae (diff) | |
| download | coreboot-f585c6eeeafb575cc64452d8519a172ffb4ffc8b.tar.gz coreboot-f585c6eeeafb575cc64452d8519a172ffb4ffc8b.tar.bz2 coreboot-f585c6eeeafb575cc64452d8519a172ffb4ffc8b.zip | |
soc/intel: Drop casts around `soc_read_pmc_base()`
The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then
casted to a pointer type for use with `read32()` and/or `write32()`. But
since commit b324df6a540d154cc9267c0398654f9142aae052 (arch/x86: Provide
readXp/writeXp helpers in arch/mmio.h), the `read32p()` and `write32p()`
functions live in `arch/mmio.h`. These functions use the `uintptr_t type
for the address parameter instead of a pointer type, and using them with
the `soc_read_pmc_base()` function allows dropping the casts to pointer.
Change-Id: Iaf16e6f23d139e6f79360d9a29576406b7b15b07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/pmc/pmclib.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index d3a21a17fd2c..a5f2dca55066 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -368,8 +368,8 @@ void pmc_clear_prsts(void) /* Read PMC base address from soc */ pmc_bar = soc_read_pmc_base(); - prsts = read32((void *)(pmc_bar + PRSTS)); - write32((void *)(pmc_bar + PRSTS), prsts); + prsts = read32p(pmc_bar + PRSTS); + write32p(pmc_bar + PRSTS, prsts); soc_clear_pm_registers(pmc_bar); } @@ -559,7 +559,7 @@ void pmc_gpe_init(void) */ if (dw0 == dw1 || dw1 == dw2) { printk(BIOS_INFO, "PMC: Using default GPE route.\n"); - gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG); + gpio_cfg = read32p(pmc_bar + GPIO_GPE_CFG); dw0 = (gpio_cfg >> GPE0_DW_SHIFT(0)) & GPE0_DWX_MASK; dw1 = (gpio_cfg >> GPE0_DW_SHIFT(1)) & GPE0_DWX_MASK; @@ -570,10 +570,10 @@ void pmc_gpe_init(void) gpio_cfg |= (uint32_t) dw2 << GPE0_DW_SHIFT(2); } - gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; + gpio_cfg_reg = read32p(pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; - write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg); + write32p(pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg); /* Set the routes in the GPIO communities as well. */ gpio_route_gpe(dw0, dw1, dw2); |