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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-14 15:06:50 +0200 |
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committer | Nick Vaccaro <nvaccaro@google.com> | 2021-08-19 18:14:59 +0000 |
commit | 6fcee7533c1a4036224339ae299e448e210ca78d (patch) | |
tree | ef3cc277bfc025e5775ebd3cab7e88d9bc02d2b7 /src/soc/intel/denverton_ns/bootblock/bootblock.c | |
parent | 891d53665b109c8bdc1b2a8f90f7a81aab024ba1 (diff) | |
download | coreboot-6fcee7533c1a4036224339ae299e448e210ca78d.tar.gz coreboot-6fcee7533c1a4036224339ae299e448e210ca78d.tar.bz2 coreboot-6fcee7533c1a4036224339ae299e448e210ca78d.zip |
soc/intel/denverton_ns: Sanity check MMCONF_BASE_ADDRESS
According to received feedback, FSP-T enables MMCONF at address
0xe0000000 with 256 busses. Sanity-check that Kconfig matches that.
Add MMCONF_BUS_NUMBER such that MCFG in ACPI will be correct.
Change-Id: I01309638a9f4ada71e5e3789db34892ed4abfa3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/denverton_ns/bootblock/bootblock.c')
-rw-r--r-- | src/soc/intel/denverton_ns/bootblock/bootblock.c | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 76db62e3fdf3..1aebab4f8329 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -1,12 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <assert.h> #include <bootblock_common.h> #include <device/pci.h> +#include <device/pci_ops.h> #include <FsptUpd.h> #include <intelblocks/fast_spi.h> #include <soc/bootblock.h> -#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/systemagent.h> #include <spi-generic.h> +#include <stdint.h> #include <console/console.h> const FSPT_UPD temp_ram_init_params = { @@ -48,6 +52,32 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) bootblock_main_with_basetime(base_timestamp); }; +static void sanity_check_pci_mmconf(void) +{ + u32 pciexbar, base = 0, length = 0; + + pciexbar = pci_io_read_config32(PCH_SA_DEV, PCIEXBAR); + assert(pciexbar & (1 << 0)); + + switch (pciexbar & MASK_PCIEXBAR_LENGTH) { + case MASK_PCIEXBAR_LENGTH_256M: + base = pciexbar & MASK_PCIEXBAR_256M; + length = 256; + break; + case MASK_PCIEXBAR_LENGTH_128M: + base = pciexbar & MASK_PCIEXBAR_128M; + length = 128; + break; + case MASK_PCIEXBAR_LENGTH_64M: + base = pciexbar & MASK_PCIEXBAR_64M; + length = 64; + break; + } + + assert(base == CONFIG_MMCONF_BASE_ADDRESS); + assert(length == CONFIG_MMCONF_BUS_NUMBER); +} + void bootblock_soc_early_init(void) { @@ -58,6 +88,8 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { + sanity_check_pci_mmconf(); + if (CONFIG(BOOTBLOCK_CONSOLE)) printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); }; |