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| author | Jeff Daly <jeffd@silicom-usa.com> | 2022-01-06 16:32:11 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-17 15:50:52 +0000 |
| commit | 2a81cab066e72f18fa269c505b417036a1091ea4 (patch) | |
| tree | c85ac704c3ca4f89020bd7e504b4e211df6aea8c /src/soc/intel/denverton_ns/csme_ie_kt.c | |
| parent | 805956bce30090ea8c047f3a5c102f38c47388ee (diff) | |
| download | coreboot-2a81cab066e72f18fa269c505b417036a1091ea4.tar.gz coreboot-2a81cab066e72f18fa269c505b417036a1091ea4.tar.bz2 coreboot-2a81cab066e72f18fa269c505b417036a1091ea4.zip | |
pci_ids.h: Make Denverton IDs consistent with other Intel SoCs
Align Denverton PCI ID define names with other Intel SoCs. Also,
update the names in SoC code accordingly.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Id4b4d971ef8f4b3ec5920209d345edbbcfae4dec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/denverton_ns/csme_ie_kt.c')
| -rw-r--r-- | src/soc/intel/denverton_ns/csme_ie_kt.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c index c10477918249..ce00627ba24d 100644 --- a/src/soc/intel/denverton_ns/csme_ie_kt.c +++ b/src/soc/intel/denverton_ns/csme_ie_kt.c @@ -59,8 +59,8 @@ static struct device_operations csme_ie_kt_ops = { }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT, - PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT, + PCI_DEVICE_ID_INTEL_DNV_ME_KT, + PCI_DEVICE_ID_INTEL_DNV_IE_KT, 0 }; |