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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-02-01 13:07:42 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 08:54:54 +0000 |
| commit | 3286848a7a013b4d4effc4e50b4b7b552236cf73 (patch) | |
| tree | 0ca1d6a306147c2d651e9385f474b6988a4f48a7 /src/soc/intel/denverton_ns/include/soc/msr.h | |
| parent | e951e8ec7f8a5a9d7b9b681526c3b16b67be15d4 (diff) | |
| download | coreboot-3286848a7a013b4d4effc4e50b4b7b552236cf73.tar.gz coreboot-3286848a7a013b4d4effc4e50b4b7b552236cf73.tar.bz2 coreboot-3286848a7a013b4d4effc4e50b4b7b552236cf73.zip | |
cpu/x86/msr: Move IA32_MISC_ENABLE bits to common place
Change-Id: I51aa300358013cb0e76704feb2115d2a7e260f8a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31193
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/denverton_ns/include/soc/msr.h')
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/msr.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 1b27eefcaa78..0d469c487183 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -96,10 +96,6 @@ #define SMRR_SUPPORTED (1 << 11) #define PRMRR_SUPPORTED (1 << 12) -/* IA32_MISC_ENABLE bits */ -#define FAST_STRINGS_ENABLE_BIT (1 << 0) -#define SPEED_STEP_ENABLE_BIT (1 << 16) - /* Read BCLK from MSR */ unsigned int bus_freq_khz(void); |