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| author | Subrata Banik <subratabanik@google.com> | 2023-01-20 16:00:26 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-22 00:31:24 +0000 |
| commit | 6d03f8986d0498d04fcf304cb247a60ef506d540 (patch) | |
| tree | 4e7248ce7ecae95d6475c643164f392aa746c5bd /src/soc/intel/denverton_ns/include/soc/pmc.h | |
| parent | 256918bd6d5977be4c020fafec0ba4401e806e25 (diff) | |
| download | coreboot-6d03f8986d0498d04fcf304cb247a60ef506d540.tar.gz coreboot-6d03f8986d0498d04fcf304cb247a60ef506d540.tar.bz2 coreboot-6d03f8986d0498d04fcf304cb247a60ef506d540.zip | |
soc/intel/denverton_ns: Add PMC macros for common code usage
This patch adds new macros (i.e. SUS Power Failure and Power Failure)
from the DNV EDS vol (doc 558579) to be able to implement common
code API to clear the power failure status bits.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6ed962eae79154a8faea382dbe8367133cb05eda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/soc/intel/denverton_ns/include/soc/pmc.h')
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/pmc.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index d5d69cb1a1c6..6e4044da2123 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -35,9 +35,13 @@ #define MASK_PMC_PWRM_BASE 0xfffff000 /* 4K alignment */ #define GEN_PMCON_A 0xA0 #define MS4V (1 << 18) +#define GBL_RST_STS (1 << 16) #define GEN_PMCON_B 0xA4 +#define GEN_PMCON_B_SUS_PWR_FLR 0x4000 +#define SUS_PWR_FLR GEN_PMCON_B_SUS_PWR_FLR #define GEN_PMCON_B_RTC_PWR_STS 0x04 #define GEN_PMCON_B_PWR_FLR 0x02 +#define PWR_FLR GEN_PMCON_B_PWR_FLR #define GEN_PMCON_B_AFTERG3_EN 0x00 #define ETR3 0xAC #define ETR3_CF9LOCK BIT31 ///< CF9h Lockdown |