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| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-10-04 16:59:49 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-10-13 18:05:05 +0000 |
| commit | 2353cd9936702c6e556a9f810f180eced1e113d9 (patch) | |
| tree | 6b753a7a60bd1bcca7439287e63569f8a352ce05 /src/soc/intel/denverton_ns | |
| parent | 51254ee9397a535f5e51d9b12702b1a385e40f0e (diff) | |
| download | coreboot-2353cd9936702c6e556a9f810f180eced1e113d9.tar.gz coreboot-2353cd9936702c6e556a9f810f180eced1e113d9.tar.bz2 coreboot-2353cd9936702c6e556a9f810f180eced1e113d9.zip | |
soc/intel: drop P_BLK support
P_BLK is legacy and superseded by ACPI _CST. Also, the implementation
for most platforms in soc/intel is broken. Thus, drop it.
For APL the IO redirection is kept since it's used as replacement for
the broken MWAIT instructions.
Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/denverton_ns')
| -rw-r--r-- | src/soc/intel/denverton_ns/acpi.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/msr.h | 1 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 4384cadd9e73..a28da4813467 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -102,9 +102,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; /* PM2 Control Registers */ diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 89caf44c17b0..21f3e7b41f55 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -7,7 +7,6 @@ #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL #define FEATURE_CONFIG_LOCK (1 << 0) |