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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-11-15 17:25:54 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-12-15 12:11:04 +0000 |
| commit | 3990da0bfe18e3b76751fd35fef9e5ec55c2fd29 (patch) | |
| tree | 666dfe2df666df37759a18938ccb06b81f9c62d2 /src/soc/intel/denverton_ns | |
| parent | fd13fb54ac8ff7bbd57a6dc9cc56219f543c4e7c (diff) | |
| download | coreboot-3990da0bfe18e3b76751fd35fef9e5ec55c2fd29.tar.gz coreboot-3990da0bfe18e3b76751fd35fef9e5ec55c2fd29.tar.bz2 coreboot-3990da0bfe18e3b76751fd35fef9e5ec55c2fd29.zip | |
soc/intel/denverton_ns: Fix MRC_RW_CACHE
It is required to set WPD (Write Protect Disable) bit
to make it possible to use MRC_RW_CACHE region with
CACHE_MRC_SETTINGS=y.
Change-Id: Iacab44b00d08c9bdc18bc3bdcb88833634c0b02e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/denverton_ns')
| -rw-r--r-- | src/soc/intel/denverton_ns/bootblock/bootblock.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index cb2503ae401a..0846c8e474b5 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -84,6 +84,7 @@ void bootblock_soc_early_init(void) #if (CONFIG(CONSOLE_SERIAL)) early_uart_init(); #endif + fast_spi_early_init(DEFAULT_SPI_BASE); }; void bootblock_soc_init(void) |