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| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-25 00:10:30 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-10-17 13:59:04 +0000 |
| commit | 0e905801f8ff6c10b20625e31d851920b3f4c4f2 (patch) | |
| tree | e18e0919b8784f450ecdcab2099ab426e1da91af /src/soc/intel/elkhartlake/acpi/pci_irqs.asl | |
| parent | 68bacc210945ef7d65dd542765c3be997caf7b4d (diff) | |
| download | coreboot-0e905801f8ff6c10b20625e31d851920b3f4c4f2.tar.gz coreboot-0e905801f8ff6c10b20625e31d851920b3f4c4f2.tar.bz2 coreboot-0e905801f8ff6c10b20625e31d851920b3f4c4f2.zip | |
soc/intel: transition full control over PM Timer from FSP to coreboot
Set `EnableTcoTimer=1` in order to keep FSP from
1) enabling ACPI Timer emulation in uCode.
2) disabling the PM ACPI Timer.
Both actions are now done in coreboot.
`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.
Change-Id: I8005daed732c031980ccc379375ff5b09df8dac1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
Diffstat (limited to 'src/soc/intel/elkhartlake/acpi/pci_irqs.asl')
0 files changed, 0 insertions, 0 deletions