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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-09 14:33:15 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-16 06:53:46 +0000 |
| commit | 08769c6d1404c1be0333273d8b988544750ce87d (patch) | |
| tree | ef37aeb920efea81b84ecf50c2ab990c09541b30 /src/soc/intel/elkhartlake | |
| parent | 159520ed7881d1be2fdd02ee13040e8e21a9833c (diff) | |
| download | coreboot-08769c6d1404c1be0333273d8b988544750ce87d.tar.gz coreboot-08769c6d1404c1be0333273d8b988544750ce87d.tar.bz2 coreboot-08769c6d1404c1be0333273d8b988544750ce87d.zip | |
soc/intel/*: Use SSDT to pass A4GB and A4GS
GNVS is more fragile as you need to keep struct elements in sync with
ASL code.
Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/elkhartlake')
| -rw-r--r-- | src/soc/intel/elkhartlake/acpi.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.c | 2 |
2 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 59a9adba79cb..9f08acd60feb 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -243,9 +243,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; - - /* Fill in Above 4GB MMIO resource */ - sa_fill_gnvs(gnvs); } int soc_madt_sci_irq_polarity(int sci) diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c index c138a1fe456a..03f9cc9b0f88 100644 --- a/src/soc/intel/elkhartlake/chip.c +++ b/src/soc/intel/elkhartlake/chip.c @@ -9,6 +9,7 @@ #include <intelblocks/gpio.h> #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> +#include <intelblocks/systemagent.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> @@ -134,6 +135,7 @@ static struct device_operations pci_domain_ops = { .scan_bus = &pci_domain_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = &soc_acpi_name, + .acpi_fill_ssdt = ssdt_set_above_4g_pci, #endif }; |