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| author | Subrata Banik <subratabanik@google.com> | 2022-01-28 02:05:15 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-02-02 07:09:28 +0000 |
| commit | 32e06732322765819e5bf54167d3159275f7dfa8 (patch) | |
| tree | c5e67bf063d178ed1c6cf1c0a82b46600e38c49b /src/soc/intel/elkhartlake | |
| parent | 736f9cced0f060a333a5efdc499607350554b9c7 (diff) | |
| download | coreboot-32e06732322765819e5bf54167d3159275f7dfa8.tar.gz coreboot-32e06732322765819e5bf54167d3159275f7dfa8.tar.bz2 coreboot-32e06732322765819e5bf54167d3159275f7dfa8.zip | |
soc/intel/common/cse: Rework heci_disable function
This patch provides the possible options for SoC users to choose the
applicable interface to make HECI1 function disable at pre-boot.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for
disabling heci1 using non-posted sideband write (inside SMM) after
FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for
disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH
onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for
disabling heci1 using private configuration register (PCR) write.
Applicable for SoC platform prior to CNL PCH.
Additionally, add PID_CSME0 macro for SKL, Xeon_SP and APL to fix the
compilation failure.
Finally, rename heci_disable() function to heci1_disable() to make it
more meaningful.
BUG=none
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/elkhartlake')
| -rw-r--r-- | src/soc/intel/elkhartlake/smihandler.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/elkhartlake/smihandler.c b/src/soc/intel/elkhartlake/smihandler.c index e3c5012a5fe4..eb5a57642f14 100644 --- a/src/soc/intel/elkhartlake/smihandler.c +++ b/src/soc/intel/elkhartlake/smihandler.c @@ -17,7 +17,7 @@ void smihandler_soc_at_finalize(void) { if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) - heci_disable(); + heci1_disable(); } const smi_handler_t southbridge_smi[SMI_STS_BITS] = { |