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| author | Werner Zeh <werner.zeh@siemens.com> | 2022-02-11 06:50:57 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 17:08:10 +0000 |
| commit | 6c5efcd26856aef56dd88c231b6e9dc453e80f71 (patch) | |
| tree | 8c74728ffdc60dfd48cb36e914da7022ab10400b /src/soc/intel/elkhartlake | |
| parent | bd842a9b92c88f73a4097b033b5784f8bbf73cb5 (diff) | |
| download | coreboot-6c5efcd26856aef56dd88c231b6e9dc453e80f71.tar.gz coreboot-6c5efcd26856aef56dd88c231b6e9dc453e80f71.tar.bz2 coreboot-6c5efcd26856aef56dd88c231b6e9dc453e80f71.zip | |
soc/intel/elkhartlake: Fix PCR ID for eSPI
According to the Datasheet Volume 1 (doc #636112, [1]) the PCR port ID
for eSPI is 0x72 (see chapter 25.2.2). Fix it in the header file.
[1]: https://cdrdv2.intel.com/v1/dl/getContent/636112?explicitVersion=true
Test=Read and modify PCR registers of eSPI controller.
Change-Id: I5b07ef0f3a285f981791b1f4b4cdbda98ccf05ad
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61841
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/elkhartlake')
| -rw-r--r-- | src/soc/intel/elkhartlake/include/soc/pcr_ids.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/elkhartlake/include/soc/pcr_ids.h b/src/soc/intel/elkhartlake/include/soc/pcr_ids.h index 20488e5b8800..75862a6e0e5c 100644 --- a/src/soc/intel/elkhartlake/include/soc/pcr_ids.h +++ b/src/soc/intel/elkhartlake/include/soc/pcr_ids.h @@ -25,7 +25,7 @@ #define PID_PSF4 0xbd #define PID_RTC 0xc3 #define PID_ITSS 0xc4 -#define PID_ESPI 0xc7 +#define PID_ESPI 0x72 #define PID_SERIALIO 0xcb #endif |