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| author | Angel Pons <th3fanbus@gmail.com> | 2022-05-16 16:21:51 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-17 21:08:47 +0000 |
| commit | da541327d2ecfc9043205a7bd81c0ed71c4313fa (patch) | |
| tree | f8f915a71c748ab9e871a122340ad6ddf4109ae5 /src/soc/intel/elkhartlake | |
| parent | 46af7f7442f53939130ed2eda2c00bb72cfa7746 (diff) | |
| download | coreboot-da541327d2ecfc9043205a7bd81c0ed71c4313fa.tar.gz coreboot-da541327d2ecfc9043205a7bd81c0ed71c4313fa.tar.bz2 coreboot-da541327d2ecfc9043205a7bd81c0ed71c4313fa.zip | |
soc/intel/elkhartlake: Enable SMBus depending on dev state
Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's
state in the devicetree. This avoids having to manually make sure the
SMBus PCI device and the `SmbusEnable` setting are in sync.
Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/elkhartlake')
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/romstage/fsp_params.c | 3 |
2 files changed, 1 insertions, 5 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 3e1d56e17edc..8764657b19fd 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -227,9 +227,6 @@ struct soc_intel_elkhartlake_config { /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; - /* SMBus */ - uint8_t SmbusEnable; - /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; uint8_t ScsEmmcDdr50Enabled; diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index b8aaca78db3f..5c8c99595961 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -64,8 +64,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->PchMasterClockGating = 1; m_cfg->PchMasterPowerGating = 1; - /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; + m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS); /* Set debug probe type */ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT; |