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| author | Werner Zeh <werner.zeh@siemens.com> | 2017-10-16 08:37:28 +0200 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-19 15:13:40 +0000 |
| commit | 4bf11ce2b5de81ec0bd6799f4830a48c7376c122 (patch) | |
| tree | d2e34db2f81666fcd969930a2f2565e8e64cc045 /src/soc/intel/fsp_broadwell_de/romstage/romstage.c | |
| parent | e77d588ee46bfdff1a152f166eca84e3c5827665 (diff) | |
| download | coreboot-4bf11ce2b5de81ec0bd6799f4830a48c7376c122.tar.gz coreboot-4bf11ce2b5de81ec0bd6799f4830a48c7376c122.tar.bz2 coreboot-4bf11ce2b5de81ec0bd6799f4830a48c7376c122.zip | |
soc/fsp_broadwell_de: Add support for GPIO handling
Add functionality to initialize, set and read back GPIOs on FSP based
Broadwell-DE implementation.
Change-Id: Ibbd86e2142bbf5772eb4a91ebb9166c31d52476e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 5754ec00a5a1..d5d0a96b565e 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2017 Siemens AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,6 +33,7 @@ #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/romstage.h> +#include <soc/gpio.h> #include <build.h> static void init_rtc(void) @@ -45,6 +47,16 @@ static void init_rtc(void) cmos_init(gen_pmcon3 & RTC_PWR_STS); } +/* Set up IO address range and enable it for the GPIO block. */ +static void setup_gpio_io_address(void) +{ + pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), GPIO_BASE_ADR_OFFSET, + GPIO_BASE_ADDRESS); + pci_write_config8(PCI_DEV(0, LPC_DEV, LPC_FUNC), GPIO_CTRL_OFFSET, + GPIO_DECODE_ENABLE); +} + + /* Entry from cache-as-ram.inc. */ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) { @@ -58,6 +70,7 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) } console_init(); init_rtc(); + setup_gpio_io_address(); /* Call into mainboard. */ post_code(0x41); |