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| author | Subrata Banik <subrata.banik@intel.com> | 2019-07-08 14:49:22 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-07-11 05:57:41 +0000 |
| commit | 10a9432cc2ad77234442bd639194c5a80050854e (patch) | |
| tree | ce6f68feab9582d2ab62765cd0d9a3262bb62b69 /src/soc/intel/icelake/fsp_params.c | |
| parent | 5b9948140f97eceb47ba026d7bad6dfa2a3c483d (diff) | |
| download | coreboot-10a9432cc2ad77234442bd639194c5a80050854e.tar.gz coreboot-10a9432cc2ad77234442bd639194c5a80050854e.tar.bz2 coreboot-10a9432cc2ad77234442bd639194c5a80050854e.zip | |
soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer
This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer
for better code sharing. Also ported CB:33512 for SPT and ICP PCH.
Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/icelake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/icelake/fsp_params.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 8b65a8973115..03b00d94fb43 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -124,6 +124,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGatingOnS3 = 1; + /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; |