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author | Subrata Banik <subrata.banik@intel.com> | 2021-06-21 18:07:50 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2021-06-23 08:25:11 +0000 |
commit | 1a5d4120e63015b4e6024f37f77c0c8af2177a65 (patch) | |
tree | 2463de73b8e5bba2b2010f40e76f99657c71ec40 /src/soc/intel/icelake/fsp_params.c | |
parent | d41a5ae4890f40da060bfd73fda344b4c5edab93 (diff) | |
download | coreboot-1a5d4120e63015b4e6024f37f77c0c8af2177a65.tar.gz coreboot-1a5d4120e63015b4e6024f37f77c0c8af2177a65.tar.bz2 coreboot-1a5d4120e63015b4e6024f37f77c0c8af2177a65.zip |
soc/intel/icelake: Make use of is_devfn_enabled() function
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type
(struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with
is_devfn_enabled() call.
4. Leave SATA, eMMC controller FSP UPDs at default state if
controller is not enabled and FSP UPDs are set to disable.
TEST=Able to build and boot without any regression seen on ICLRVP.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Id6861af3b5d1ce4f44b6d2109301bd4f5857f324
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/icelake/fsp_params.c')
-rw-r--r-- | src/soc/intel/icelake/fsp_params.c | 36 |
1 files changed, 8 insertions, 28 deletions
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 395bca8abe6a..a849881bbd9a 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -55,11 +55,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) mainboard_silicon_init_params(params); - dev = pcidev_path_on_root(SA_DEVFN_IGD); - if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) - params->PeiGraphicsPeimInit = 1; - else - params->PeiGraphicsPeimInit = 0; + params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); params->PavpEnable = CONFIG(PAVP); @@ -68,11 +64,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->CnviBtAudioOffload = config->CnviBtAudioOffload; /* SATA */ - dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); - if (!dev) - params->SataEnable = 0; - else { - params->SataEnable = dev->enabled; + params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); + if (params->SataEnable) { params->SataMode = config->SataMode; params->SataSalpSupport = config->SataSalpSupport; memcpy(params->SataPortsEnable, config->SataPortsEnable, @@ -82,11 +75,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* Lan */ - dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); - if (!dev) - params->PchLanEnable = 0; - else - params->PchLanEnable = dev->enabled; + params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); /* Audio */ params->PchHdaDspEnable = config->PchHdaDspEnable; @@ -166,11 +155,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(config->PcieClkSrcClkReq)); /* eMMC */ - dev = pcidev_on_root(PCH_DEV_SLOT_STORAGE, 0); - if (!dev) - params->ScsEmmcEnabled = 0; - else { - params->ScsEmmcEnabled = dev->enabled; + params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); + if (params->ScsEmmcEnabled) { params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; params->EmmcUseCustomDlls = config->EmmcUseCustomDlls; if (config->EmmcUseCustomDlls == 1) { @@ -190,14 +176,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* SD */ - dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 5); - if (!dev) - params->ScsSdCardEnabled = 0; - else { - params->ScsSdCardEnabled = dev->enabled; - params->SdCardPowerEnableActiveHigh = - config->SdCardPowerEnableActiveHigh; - } + params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD); + params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh; params->Heci3Enabled = config->Heci3Enabled; params->Device4Enable = config->Device4Enable; |