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| author | Subrata Banik <subrata.banik@intel.com> | 2018-10-31 23:08:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-06-13 04:38:08 +0000 |
| commit | 3d152ac388fa43b4c3d1bfeedcb6a40f1479ace3 (patch) | |
| tree | ca39c17047de8a3059cea7314f95910f2b45a8a1 /src/soc/intel/icelake/fsp_params.c | |
| parent | 8a70918b8a78d8d5cd27e830cc4ae496b10d4f32 (diff) | |
| download | coreboot-3d152ac388fa43b4c3d1bfeedcb6a40f1479ace3.tar.gz coreboot-3d152ac388fa43b4c3d1bfeedcb6a40f1479ace3.tar.bz2 coreboot-3d152ac388fa43b4c3d1bfeedcb6a40f1479ace3.zip | |
soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI,
hence modify SoC code to reflect the same.
This patch replaces all SoC specific PCI LPC references with ESPI
except anything that touches intel common code block.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Diffstat (limited to 'src/soc/intel/icelake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/icelake/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 127507b45a3c..ac7edd2dbbe7 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -102,7 +102,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* Lan */ - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 6); + dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); if (!dev) params->PchLanEnable = 0; else |