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| author | Subrata Banik <subrata.banik@intel.com> | 2020-02-19 19:09:06 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-24 13:17:14 +0000 |
| commit | 9d667906f3c0029dbea41580a0d0961cf1ab2fc9 (patch) | |
| tree | d640ffd3fe72f1f74605834e62d98de414ea7f1c /src/soc/intel/icelake/fsp_params.c | |
| parent | f07d3b45856fb3cb62d684e526c4fd2af76ee33f (diff) | |
| download | coreboot-9d667906f3c0029dbea41580a0d0961cf1ab2fc9.tar.gz coreboot-9d667906f3c0029dbea41580a0d0961cf1ab2fc9.tar.bz2 coreboot-9d667906f3c0029dbea41580a0d0961cf1ab2fc9.zip | |
soc/intel/icelake: Skip FSP-S IGD related UPD override
Default FSP values for "GtFreqMax" and "CdClock" UPDs are "Auto", hence
related FSP-S UPD override can be avoided from coreboot.
As per FSP-S UPD Header (FspsUpd.h)
/** Offset 0x020E - GT Frequency Limit
0xFF: Auto(Default)
**/
UINT8 GtFreqMax;
/** Offset 0x0209 - CdClock Frequency selection
0: (Default) Auto
**/
UINT8 CdClock;
TEST=Able to get Pre-OS display on ICLRVP and Dragonegg platform.
Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/soc/intel/icelake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/icelake/fsp_params.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 448b82c7d85a..7514be107df8 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -96,10 +96,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PeiGraphicsPeimInit = 1; else params->PeiGraphicsPeimInit = 0; - if (dev && dev->enabled) { - params->GtFreqMax = 2; - params->CdClock = 3; - } /* Unlock upper 8 bytes of RTC RAM */ params->PchLockDownRtcMemoryLock = 0; |