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| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-15 16:35:56 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-09-23 06:31:58 +0000 |
| commit | 46ef53621265feeeebca475a0078f6bd301fcb35 (patch) | |
| tree | 97f7d3e1de612b3767da1948cabfc303cd35e104 /src/soc/intel/icelake/include/soc/gpio_defs.h | |
| parent | 85610d8d86de10cdb8c82b61290501ee0b3cf742 (diff) | |
| download | coreboot-46ef53621265feeeebca475a0078f6bd301fcb35.tar.gz coreboot-46ef53621265feeeebca475a0078f6bd301fcb35.tar.bz2 coreboot-46ef53621265feeeebca475a0078f6bd301fcb35.zip | |
soc/intel/icelake: correct wrong gpio SMI register base offsets
Reference: Intel doc# 341081-002.
Change-Id: If6e0503cc042c26c4077b8b32bb447d4e3a9bb6a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/icelake/include/soc/gpio_defs.h')
| -rw-r--r-- | src/soc/intel/icelake/include/soc/gpio_defs.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index b9238a5d2b64..1291304384c5 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -253,8 +253,8 @@ #define HOSTSW_OWN_REG_0 0xb0 #define GPI_INT_STS_0 0x100 #define GPI_INT_EN_0 0x110 -#define GPI_SMI_STS_0 0x180 -#define GPI_SMI_EN_0 0x1A0 +#define GPI_SMI_STS_0 0x170 +#define GPI_SMI_EN_0 0x190 #define GPI_NMI_STS_0 0x1b0 #define GPI_NMI_EN_0 0x1d0 #define PAD_CFG_BASE 0x600 |