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| author | Subrata Banik <subrata.banik@intel.com> | 2021-06-21 18:07:50 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-06-23 08:25:11 +0000 |
| commit | 1a5d4120e63015b4e6024f37f77c0c8af2177a65 (patch) | |
| tree | 2463de73b8e5bba2b2010f40e76f99657c71ec40 /src/soc/intel/icelake/romstage/fsp_params.c | |
| parent | d41a5ae4890f40da060bfd73fda344b4c5edab93 (diff) | |
| download | coreboot-1a5d4120e63015b4e6024f37f77c0c8af2177a65.tar.gz coreboot-1a5d4120e63015b4e6024f37f77c0c8af2177a65.tar.bz2 coreboot-1a5d4120e63015b4e6024f37f77c0c8af2177a65.zip | |
soc/intel/icelake: Make use of is_devfn_enabled() function
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type
(struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with
is_devfn_enabled() call.
4. Leave SATA, eMMC controller FSP UPDs at default state if
controller is not enabled and FSP UPDs are set to disable.
TEST=Able to build and boot without any regression seen on ICLRVP.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Id6861af3b5d1ce4f44b6d2109301bd4f5857f324
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/icelake/romstage/fsp_params.c')
| -rw-r--r-- | src/soc/intel/icelake/romstage/fsp_params.c | 22 |
1 files changed, 7 insertions, 15 deletions
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index a5311d930c84..7ddf6257ac0a 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -13,18 +13,14 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_icelake_config *config) { unsigned int i; - const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); uint32_t mask = 0; - if (CONFIG(SOC_INTEL_DISABLE_IGD) || !dev || !dev->enabled) { - /* Skip IGD initialization in FSP if device is disabled */ - m_cfg->InternalGfx = 0; - m_cfg->IgdDvmt50PreAlloc = 0; - } else { - m_cfg->InternalGfx = 1; - /* Set IGD stolen size to 60MB. */ - m_cfg->IgdDvmt50PreAlloc = 0xFE; - } + /* + * If IGD is enabled, set IGD stolen size to 60MB. + * Otherwise, skip IGD init in FSP. + */ + m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD); + m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0; m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; @@ -34,11 +30,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->SkipMbpHob = 1; /* If Audio Codec is enabled, enable FSP UPD */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); - if (!dev) - m_cfg->PchHdaEnable = 0; - else - m_cfg->PchHdaEnable = dev->enabled; + m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA); for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) |