diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-06-30 23:39:27 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-06-09 02:47:17 +0000 |
| commit | 2ee8fe0094da413fe57796131d7c3b9f927f68a1 (patch) | |
| tree | 8fd622482884325759b485a9978b80d67397f40c /src/soc/intel/icelake/romstage/fsp_params.c | |
| parent | a427ff0f500b16e3a073cff6af66d9c3a562caf4 (diff) | |
| download | coreboot-2ee8fe0094da413fe57796131d7c3b9f927f68a1.tar.gz coreboot-2ee8fe0094da413fe57796131d7c3b9f927f68a1.tar.bz2 coreboot-2ee8fe0094da413fe57796131d7c3b9f927f68a1.zip | |
soc/intel/icelake: Pass FSP-M/S UPD as per ICL requirement
1. Gfx stolen memory requirement for ICL GFX
2. Enable PeiGraphicsPeim support
Change-Id: I22dd14249b7402873f1ac07bee164ee7bee36414
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31955
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/romstage/fsp_params.c')
| -rw-r--r-- | src/soc/intel/icelake/romstage/fsp_params.c | 61 |
1 files changed, 60 insertions, 1 deletions
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 69b5b7a7adb5..3c49feeccce2 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -13,13 +13,72 @@ * GNU General Public License for more details. */ +#include <assert.h> +#include <chip.h> #include <console/console.h> #include <fsp/util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> #include <soc/romstage.h> +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_icelake_config *config) +{ + unsigned int i; + const struct device *dev = pcidev_on_root(0, 0); + uint32_t mask = 0; + + /* Set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = 0xFE; + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->SaGv = config->SaGv; + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + m_cfg->RMT = config->RMT; + m_cfg->SkipMbpHob = 1; + /* If Audio Codec is enabled, enable FSP UPD */ + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; + + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->PcieRpEnableMask = mask; + m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->EnableC6Dram = config->enable_c6dram; + /* Disable BIOS Guard */ + m_cfg->BiosGuard = 0; + /* Disable Cpu Ratio Override temporary. */ + m_cfg->CpuRatio = 0; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + m_cfg->PcdDebugInterfaceFlags = + CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - /* ToDo: update with UPD override as FSP matures */ + const struct device *dev = pcidev_on_root(0, 0); + assert(dev != NULL); + const struct soc_intel_icelake_config *config = dev->chip_info; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + soc_memory_init_params(m_cfg, config); + + /* Enable SMBus controller based on config */ + m_cfg->SmbusEnable = config->SmbusEnable; + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = config->DebugConsent; + + /* Vt-D config */ + m_cfg->VtdDisable = 0; + + mainboard_memory_init_params(mupd); } __weak void mainboard_memory_init_params(FSPM_UPD *mupd) |