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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-15 12:20:08 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-21 15:51:01 +0000 |
| commit | 490546f191cf2aa1aceec97b7d0503f4fb4408f4 (patch) | |
| tree | 6c4982abda83d97c9a8afecd09b0724221b8605c /src/soc/intel/icelake/romstage/fsp_params.c | |
| parent | 1dac89633e99f57bf4abc000c1de174dd9f2563a (diff) | |
| download | coreboot-490546f191cf2aa1aceec97b7d0503f4fb4408f4.tar.gz coreboot-490546f191cf2aa1aceec97b7d0503f4fb4408f4.tar.bz2 coreboot-490546f191cf2aa1aceec97b7d0503f4fb4408f4.zip | |
soc/intel: rename get_prmrr_size
get_prmrr_size does not return the actual PRMRR size but a valid PRMRR
size with repect to the users choice in Kconfig. Thus, rename it from
`get_prmrr_size` to `get_valid_prmrr_size` to avoid confusion about what
it does.
Also fix the broken comment in cpulib.h.
Change-Id: Id243be50acb741f2c3118ddde082743d08983a53
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/icelake/romstage/fsp_params.c')
| -rw-r--r-- | src/soc/intel/icelake/romstage/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index e944c7698518..0801da23bf23 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -45,7 +45,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; |