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| author | Subrata Banik <subrata.banik@intel.com> | 2019-07-05 16:00:38 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-07-09 10:52:19 +0000 |
| commit | df29d23ee3f36d3d6a5fa0fde46beeb67554a8da (patch) | |
| tree | 93719f2cbd5fc31cbe613ba67fc703d66899e81a /src/soc/intel/icelake/romstage/fsp_params.c | |
| parent | 45564050ec00b6d4b2c5b27cf26a56b46db8df1c (diff) | |
| download | coreboot-df29d23ee3f36d3d6a5fa0fde46beeb67554a8da.tar.gz coreboot-df29d23ee3f36d3d6a5fa0fde46beeb67554a8da.tar.bz2 coreboot-df29d23ee3f36d3d6a5fa0fde46beeb67554a8da.zip | |
soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h
Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34085
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/romstage/fsp_params.c')
| -rw-r--r-- | src/soc/intel/icelake/romstage/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index fa6f9392a40f..420c427e7a78 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -14,12 +14,12 @@ */ #include <assert.h> -#include <chip.h> #include <console/console.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/romstage.h> +#include <soc/soc_chip.h> static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_icelake_config *config) |