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| author | Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> | 2021-09-15 13:22:23 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-17 22:20:05 +0000 |
| commit | 1ad9ff815610fd94820a9f1c6d4426ae49ba2846 (patch) | |
| tree | a6bb3143379f2a886d64aee8e0a40c257a298c9d /src/soc/intel/jasperlake/chip.h | |
| parent | 8d46db20a3605606e9f6b25512aa3569ce818746 (diff) | |
| download | coreboot-1ad9ff815610fd94820a9f1c6d4426ae49ba2846.tar.gz coreboot-1ad9ff815610fd94820a9f1c6d4426ae49ba2846.tar.bz2 coreboot-1ad9ff815610fd94820a9f1c6d4426ae49ba2846.zip | |
mb/google/brya/primus: add NVMe power and reset pin to early_gpio_table
NVMe needs extra time to run boot process, enable power and deassert
reset for NVMe earlier in the boot flow that primus can successfully
boot into OS with non-serial coreboot.
BUG=b:199967106
TEST=USE="project_primus" emerge-brya coreboot and verify it builds
without error.
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I9c66efe96515347502d059556052c764c1be5d09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/jasperlake/chip.h')
0 files changed, 0 insertions, 0 deletions