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| author | Eugene Myers <edmyers@tycho.nsa.gov> | 2020-10-01 14:59:27 -0400 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-12 08:49:57 +0000 |
| commit | 7979bf5d0dc7fa0abc1ba8dec1557435012faa06 (patch) | |
| tree | 52ff90be18ef857ca1399979a7b74826606afb71 /src/soc/intel/jasperlake/chip.h | |
| parent | 88352c550d2c1cd2e6f308df7a7a67d7224c43e8 (diff) | |
| download | coreboot-7979bf5d0dc7fa0abc1ba8dec1557435012faa06.tar.gz coreboot-7979bf5d0dc7fa0abc1ba8dec1557435012faa06.tar.bz2 coreboot-7979bf5d0dc7fa0abc1ba8dec1557435012faa06.zip | |
security/intel/stm: Add options for STM build
This patch adds options that support building the STM as a
part of the coreboot build. The option defaults assume that
these configuration options are set as follows:
IED_REGION_SIZE = 0x400000
SMM_RESERVED_SIZE = 0x200000
SMM_TSEG_SIZE = 0x800000
Change-Id: I80ed7cbcb93468c5ff93d089d77742ce7b671a37
Signed-off-by: Eugene Myers <cedarhouse@comcast.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/intel/jasperlake/chip.h')
0 files changed, 0 insertions, 0 deletions