diff options
| author | Chia-Ling Hou <chia-ling.hou@intel.com> | 2023-06-07 16:53:00 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-23 15:22:45 +0000 |
| commit | b5a032859aec1449b46eed60a6c6aeb9147e45a7 (patch) | |
| tree | 1fe057507bc9193485619a060990ebddc5ba8f9c /src/soc/intel/jasperlake/chip.h | |
| parent | 3dedfcbbd472fe569e06e8454db77fa8915a0a2f (diff) | |
| download | coreboot-b5a032859aec1449b46eed60a6c6aeb9147e45a7.tar.gz coreboot-b5a032859aec1449b46eed60a6c6aeb9147e45a7.tar.bz2 coreboot-b5a032859aec1449b46eed60a6c6aeb9147e45a7.zip | |
soc/intel/jasperlake: Add per-SKU power limits
Add JSL SKUs ID and add PLx from JSL PDG in project devicetree.
BUG=b:281479111
TEST=emerge-dedede coreboot and read correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Super Ni <super.ni@intel.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/soc/intel/jasperlake/chip.h')
| -rw-r--r-- | src/soc/intel/jasperlake/chip.h | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index e6b8f6805e5a..b986f18c3a32 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -3,6 +3,7 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ +#include <device/pci_ids.h> #include <drivers/i2c/designware/dw_i2c.h> #include <gpio.h> #include <drivers/intel/gma/gma.h> @@ -23,13 +24,44 @@ #define MAX_HD_AUDIO_SNDW_LINKS 4 #define MAX_HD_AUDIO_SSP_LINKS 6 +/* Types of different SKUs */ +enum soc_intel_jasperlake_power_limits { + JSL_N4500_6W_CORE, + JSL_N6000_6W_CORE, + JSL_N5100_6W_CORE, + JSL_N4505_10W_CORE, + JSL_N5105_10W_CORE, + JSL_N6005_10W_CORE, + JSL_POWER_LIMITS_COUNT +}; + +/* TDP values for different SKUs */ +enum soc_intel_jasperlake_cpu_tdps { + TDP_6W = 6, + TDP_10W = 10 +}; + +/* Mapping of different SKUs based on CPU ID and TDP values */ +static const struct { + unsigned int pci_did; + enum soc_intel_jasperlake_power_limits limits; + enum soc_intel_jasperlake_cpu_tdps cpu_tdp; +} cpuid_to_jsl[] = { + { PCI_DID_INTEL_JSL_ID_1, JSL_N4500_6W_CORE, TDP_6W }, + { PCI_DID_INTEL_JSL_ID_2, JSL_N6000_6W_CORE, TDP_6W }, + { PCI_DID_INTEL_JSL_ID_3, JSL_N5100_6W_CORE, TDP_6W }, + { PCI_DID_INTEL_JSL_ID_4, JSL_N4505_10W_CORE, TDP_10W }, + { PCI_DID_INTEL_JSL_ID_5, JSL_N5105_10W_CORE, TDP_10W }, + { PCI_DID_INTEL_JSL_ID_6, JSL_N6005_10W_CORE, TDP_10W }, +}; + struct soc_intel_jasperlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; /* Common struct containing power limits configuration information */ - struct soc_power_limits_config power_limits_config; + struct soc_power_limits_config power_limits_config[JSL_POWER_LIMITS_COUNT]; /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ |