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| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-03-25 13:20:34 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-03-28 14:08:23 +0000 |
| commit | 512b77abb582e6c2566d3873b273dd32731e7bae (patch) | |
| tree | 8807f78791588d361bd1cef00e11f6619203c713 /src/soc/intel/jasperlake/include/soc/iomap.h | |
| parent | dd7acaad27e4f99f025df7f06d71dbb49d0e399b (diff) | |
| download | coreboot-512b77abb582e6c2566d3873b273dd32731e7bae.tar.gz coreboot-512b77abb582e6c2566d3873b273dd32731e7bae.tar.bz2 coreboot-512b77abb582e6c2566d3873b273dd32731e7bae.zip | |
soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake
This is a follow-up patch to initial copy patch for Jasper Lake SoC.
Remove all Tiger Lake specfic code from Jasper Lake SoC code.
BUG=b:150217037
Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/jasperlake/include/soc/iomap.h')
| -rw-r--r-- | src/soc/intel/jasperlake/include/soc/iomap.h | 24 |
1 files changed, 2 insertions, 22 deletions
diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h index 5eda08a1321b..ef166382aced 100644 --- a/src/soc/intel/jasperlake/include/soc/iomap.h +++ b/src/soc/intel/jasperlake/include/soc/iomap.h @@ -12,14 +12,8 @@ * GNU General Public License for more details. */ -/* - * This file is created based on Intel Tiger Lake Firmware Architecture Specification - * Document number: 608531 - * Chapter number: 4 - */ - -#ifndef _SOC_TIGERLAKE_IOMAP_H_ -#define _SOC_TIGERLAKE_IOMAP_H_ +#ifndef _SOC_JASPERLAKE_IOMAP_H_ +#define _SOC_JASPERLAKE_IOMAP_H_ /* * Memory-mapped I/O registers. @@ -91,18 +85,6 @@ #define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) -#if CONFIG(SOC_INTEL_TIGERLAKE_COPY) - -#define MCH_BASE_ADDRESS 0xfedc0000 -#define MCH_BASE_SIZE 0x20000 - -#define EARLY_GSPI_BASE_ADDRESS 0xfe030000 - -#define EARLY_I2C_BASE_ADDRESS 0xfe020000 -#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) - -#else /* CONFIG_SOC_INTEL_JASPERLAKE_COPY */ - #define MCH_BASE_ADDRESS 0xfea80000 #define MCH_BASE_SIZE 0x8000 @@ -111,8 +93,6 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) -#endif - /* * I/O port address space */ |