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| author | Nico Huber <nico.h@gmx.de> | 2024-01-12 16:22:19 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-19 13:18:17 +0000 |
| commit | 3d80d14cd4ed82e74057cea884dcb9bb7588c076 (patch) | |
| tree | 2b871fd211af0a239a0926f28c787e3cd406cc90 /src/soc/intel/jasperlake/include/soc/pcie.h | |
| parent | 9bf38c7d672dbfe0771a15574a7e0c59f38c139c (diff) | |
| download | coreboot-3d80d14cd4ed82e74057cea884dcb9bb7588c076.tar.gz coreboot-3d80d14cd4ed82e74057cea884dcb9bb7588c076.tar.bz2 coreboot-3d80d14cd4ed82e74057cea884dcb9bb7588c076.zip | |
soc/intel/jasperlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/jasperlake/include/soc/pcie.h')
| -rw-r--r-- | src/soc/intel/jasperlake/include/soc/pcie.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/include/soc/pcie.h b/src/soc/intel/jasperlake/include/soc/pcie.h new file mode 100644 index 000000000000..17710cc80861 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pcie.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_JASPERLAKE_PCIE_H__ +#define __SOC_JASPERLAKE_PCIE_H__ + +#include <intelblocks/pcie_rp.h> + +extern const struct pcie_rp_group pch_rp_groups[]; + +#endif /* __SOC_JASPERLAKE_PCIE_H__ */ |