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authorSubrata Banik <subratabanik@google.com>2022-11-04 22:14:38 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-11-08 14:12:27 +0000
commitc8b9608154522c38dbd47c09aa08585f1b667c05 (patch)
tree305f2a80ba3312235c147d703db8704f598dc147 /src/soc/intel/jasperlake/pmc.c
parentc3d5b9d74f80b74ef4773f4d4b2a75ff0a438121 (diff)
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soc/intel: Use `PWRMBASE` over static `Index 0` for PMC
This patch replaces static index 0 for PMC read resources with PCI configuration offset 0x10 (PWRMBASE). TEST=Able to build and boot Google, Rex to OS. Without this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 With this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iee2523876a8045e70effd5824afc327d1113038b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/jasperlake/pmc.c')
-rw-r--r--src/soc/intel/jasperlake/pmc.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c
index 4a4834547cc3..8f79f0c41e46 100644
--- a/src/soc/intel/jasperlake/pmc.c
+++ b/src/soc/intel/jasperlake/pmc.c
@@ -71,7 +71,8 @@ static void soc_pmc_read_resources(struct device *dev)
{
struct resource *res;
- mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
+ mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB,
+ PCH_PWRM_BASE_SIZE / KiB);
res = new_resource(dev, 1);
res->base = (resource_t)ACPI_BASE_ADDRESS;