diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-16 02:57:30 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-11 12:28:52 +0000 |
| commit | 06e33226b3cfd2c642f769440b7d1b5191c99d6b (patch) | |
| tree | 4b4f072335758951e06d997ec60782d8240069c7 /src/soc/intel/quark/Kconfig | |
| parent | b1c57d1bebb6dd516afa2e85a3f8082a6c77f8ec (diff) | |
| download | coreboot-06e33226b3cfd2c642f769440b7d1b5191c99d6b.tar.gz coreboot-06e33226b3cfd2c642f769440b7d1b5191c99d6b.tar.bz2 coreboot-06e33226b3cfd2c642f769440b7d1b5191c99d6b.zip | |
mb/intel/galileo: Drop the FSP1.1 option
This board is EOL and has FSP2.0 support, so drop the older
version.
Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/quark/Kconfig')
| -rw-r--r-- | src/soc/intel/quark/Kconfig | 49 |
1 files changed, 0 insertions, 49 deletions
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index beed8cd6d381..2a0c13297e88 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -107,17 +107,6 @@ config ENABLE_DEBUG_LED_ESRAM Indicate that ESRAM has been successfully initialized. If the SD LED does not light then the ESRAM initialization needs to be debugged. -config ENABLE_DEBUG_LED_FINDFSP - bool "SD LED indicates fsp.bin file was found" - depends on PLATFORM_USES_FSP1_1 - default n - select ENABLE_DEBUG_LED - help - Indicate that fsp.bin was found. If the SD LED does not light then - the code between ESRAM initialization through find_fsp needs to - debugged. Start by verifying that the correct fsp.bin is in the - image. - config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY bool "SD LED indicates bootblock.c successfully entered" default n @@ -160,12 +149,10 @@ config ENABLE_DEBUG_LED_SOC_INIT_ENTRY config DCACHE_RAM_BASE hex - default 0x80070000 if PLATFORM_USES_FSP1_1 default 0x80000000 config DCACHE_RAM_SIZE hex - default 0x8000 if PLATFORM_USES_FSP1_1 default 0x40000 config DISPLAY_ESRAM_LAYOUT @@ -197,48 +184,12 @@ config CBFS_SIZE # SoC code to boot coreboot and its payload. ##### -config ADD_FSP_RAW_BIN - bool "Add the Intel FSP binary to the flash image without relocation" - default n - depends on PLATFORM_USES_FSP1_1 - help - Select this option to add an Intel FSP binary to - the resulting coreboot image. - - Note: Without this binary, coreboot builds relying on the FSP - will not boot - -config FSP_FILE - string "Intel FSP binary path and filename" - default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP.fd" - depends on PLATFORM_USES_FSP1_1 - depends on ADD_FSP_RAW_BIN - help - The path and filename of the Intel FSP binary for this platform. - -config FSP_LOC - hex - default 0xfff80000 - depends on PLATFORM_USES_FSP1_1 - help - The location in CBFS that the FSP is located. This must match the - value that is set in the FSP binary. If the FSP needs to be moved, - rebase the FSP with Intel's BCT (tool). - config FSP_ESRAM_LOC hex - default 0x80000000 if PLATFORM_USES_FSP1_1 default 0x80040000 help The location in ESRAM where a copy of the FSP binary is placed. -config RELOCATE_FSP_INTO_DRAM - bool "Relocate FSP into DRAM" - default n - depends on PLATFORM_USES_FSP1_1 - help - Relocate the FSP binary into DRAM before the call to SiliconInit. - config FSP_M_FILE string depends on PLATFORM_USES_FSP2_0 |