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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-02-07 14:52:22 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-02-10 03:11:45 +0100 |
| commit | 43cdff6b453e0563414a020c2bab69a841a8f2e8 (patch) | |
| tree | 7dcd1466fe13b2be914b3af473fedf2e353ccd35 /src/soc/intel/quark/include/soc/pci_devs.h | |
| parent | 3968653f25d9c2147f0b74aa4467a555204a4c9b (diff) | |
| download | coreboot-43cdff6b453e0563414a020c2bab69a841a8f2e8.tar.gz coreboot-43cdff6b453e0563414a020c2bab69a841a8f2e8.tar.bz2 coreboot-43cdff6b453e0563414a020c2bab69a841a8f2e8.zip | |
soc/intel/quark: MTRR support
Add the SoC specific routines to access the MTRR registers. These
registers exist in the host bridge and are not accessible via the
rdmsr/wrmsr instructions.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select DISPLAY_MTRRS"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* The message "FSP TempRamInit successful" is displayed
Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13530
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Diffstat (limited to 'src/soc/intel/quark/include/soc/pci_devs.h')
| -rw-r--r-- | src/soc/intel/quark/include/soc/pci_devs.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 0543a05b5353..4ab23b9745ce 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -18,6 +18,12 @@ #ifndef _QUARK_PCI_DEVS_H_ #define _QUARK_PCI_DEVS_H_ +#include <device/pci.h> +#include <soc/QuarkNcSocId.h> + +/* DEVICE 0 (Memroy Controller Hub) */ +#define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN) + /* IO Fabric 1 */ #define SIO1_DEV 0x14 # define HSUART1_DEV SIO1_DEV |