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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-04-29 15:16:54 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-05-31 21:50:31 +0200 |
| commit | 5ef051a53a03d537b6feab4e85edb69835eb6998 (patch) | |
| tree | eb2c8089bf5fc987f6bafe4587be4db0aef66005 /src/soc/intel/quark/include/soc/pci_devs.h | |
| parent | a87fcabd2efe49c8035b76146401e190a0ea6593 (diff) | |
| download | coreboot-5ef051a53a03d537b6feab4e85edb69835eb6998.tar.gz coreboot-5ef051a53a03d537b6feab4e85edb69835eb6998.tar.bz2 coreboot-5ef051a53a03d537b6feab4e85edb69835eb6998.zip | |
soc/intel/quark: Add PCIe reset support
Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into
coreboot.
Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14944
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/include/soc/pci_devs.h')
| -rw-r--r-- | src/soc/intel/quark/include/soc/pci_devs.h | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 67d8d32febc4..ff9d65f6efe2 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -18,9 +18,8 @@ #ifndef _QUARK_PCI_DEVS_H_ #define _QUARK_PCI_DEVS_H_ -#include <arch/io.h> #include <device/pci.h> -#include <soc/QuarkNcSocId.h> +#include <soc/reg_access.h> /* DEVICE 0 (Memory Controller Hub) */ #define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN) @@ -29,6 +28,8 @@ #define I2CGPIO_DEVID 0x0934 #define HSUART_DEVID 0x0936 #define EHCI_DEVID 0x0939 +#define PCIE_PORT0_DEVID 0x11c3 +#define PCIE_PORT1_DEVID 0x11c4 /* IO Fabric 1 */ #define SIO1_DEV 0x14 @@ -45,6 +46,18 @@ #define I2CGPIO_DEV_FUNC PCI_DEVFN(I2CGPIO_DEV, I2CGPIO_FUNC) #define I2CGPIO_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, I2CGPIO_DEV, I2CGPIO_FUNC) +/* PCIe Ports */ +#define PCIE_DEV 0x17 +#define PCIE_PORT0_DEV PCIE_DEV +#define PCIE_PORT0_FUNC 0 +#define PCIE_PORT0_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT0_FUNC) +#define PCIE_PORT0_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT0_FUNC) + +#define PCIE_PORT1_DEV PCIE_DEV +#define PCIE_PORT1_FUNC 1 +#define PCIE_PORT1_DEV_FUNC DEV_FUNC(PCIE_DEV,PCIE_PORT1_FUNC) +#define PCIE_PORT1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT1_FUNC) + /* Platform Controller Unit */ #define LPC_DEV PCI_DEVICE_NUMBER_QNC_LPC #define LPC_FUNC PCI_FUNCTION_NUMBER_QNC_LPC |