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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-05-24 13:23:26 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-06-20 18:11:07 +0200 |
| commit | d9351099ef5ca58a6153da1b782178bda22bc879 (patch) | |
| tree | 9ba7393c6a9083d094f5d9c4fc80f61c1316d56e /src/soc/intel/quark/include/soc/pci_devs.h | |
| parent | 0cae6e9e5d1be31daf80894dbf5f01880c786bbb (diff) | |
| download | coreboot-d9351099ef5ca58a6153da1b782178bda22bc879.tar.gz coreboot-d9351099ef5ca58a6153da1b782178bda22bc879.tar.bz2 coreboot-d9351099ef5ca58a6153da1b782178bda22bc879.zip | |
soc/intel/quark: Add legacy SPI flash controller driver
Add SPI driver code for the legacy SPI flash controller. Enable erase
and write support allowing coreboot to save non-volatile data into
the SPI flash.
TEST=Build and run on Galileo Gen2.
Change-Id: I8f38c955d7c42a1e58728c728d0cecc36556de5c
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/include/soc/pci_devs.h')
| -rw-r--r-- | src/soc/intel/quark/include/soc/pci_devs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index a4e7a87fd2db..1e1740286822 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -28,6 +28,7 @@ #define I2CGPIO_DEVID 0x0934 #define HSUART_DEVID 0x0936 #define EHCI_DEVID 0x0939 +#define LPC_DEVID 0X095E #define PCIE_PORT0_DEVID 0x11c3 #define PCIE_PORT1_DEVID 0x11c4 |