soc/intel: Move fill_postcar_frame to memmap.c

Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 27 insertions, 0 deletions

diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c
index d67856cc74fc..b8b85063a89d 100644
--- a/src/soc/intel/quark/memmap.c
+++ b/src/soc/intel/quark/memmap.c
@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <cbmem.h>
 #include <soc/reg_access.h>
 
@@ -32,3 +34,28 @@ void *cbmem_top(void)
 	/* Return the top of memory */
 	return (void *)top_of_memory;
 }
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+	uintptr_t top_of_ram;
+	uintptr_t top_of_low_usable_memory;
+
+	/* Locate the top of RAM */
+	top_of_low_usable_memory = (uintptr_t) cbmem_top();
+	top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB);
+
+	/* Cache postcar and ramstage */
+	postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB,
+		MTRR_TYPE_WRBACK);
+
+	/* Cache RMU area */
+	postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory,
+		0x10000, MTRR_TYPE_WRTHROUGH);
+
+	/* Cache ESRAM */
+	postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
+
+	pcf->skip_common_mtrr = 1;
+	/* Cache SPI flash - Write protect not supported */
+	postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH);
+}