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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-09 22:53:52 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-09 07:53:23 +0000 |
| commit | cc93c6e47480de06ce87705a93bc46d806cabbb3 (patch) | |
| tree | 4fa56de3a3e885246d3892c6897d954bf2e3ffb3 /src/soc/intel/quark | |
| parent | 4949a3dd626560aa504cee18d936d0d7602becfa (diff) | |
| download | coreboot-cc93c6e47480de06ce87705a93bc46d806cabbb3.tar.gz coreboot-cc93c6e47480de06ce87705a93bc46d806cabbb3.tar.bz2 coreboot-cc93c6e47480de06ce87705a93bc46d806cabbb3.zip | |
soc/amd,intel: Drop s3_resume parameter on FSP-S functions
ACPI S3 is a global state and it is no longer needed to
pass it as a parameter.
Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/intel/quark')
| -rw-r--r-- | src/soc/intel/quark/chip.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 33033a98b637..e613ced2cd9b 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -2,7 +2,6 @@ #include <assert.h> #include <device/device.h> -#include <romstage_handoff.h> #include <soc/ramstage.h> #include <soc/reg_access.h> @@ -103,7 +102,7 @@ static void chip_init(void *chip_info) | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); /* Perform silicon specific init. */ - fsp_silicon_init(romstage_handoff_is_resume()); + fsp_silicon_init(); } static struct device_operations pci_domain_ops = { |