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| author | Felix Singer <felixsinger@posteo.net> | 2020-07-29 20:48:08 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-08-07 21:30:02 +0000 |
| commit | 9c1c00968c943659bab2a817892e5a9be9dfb7c0 (patch) | |
| tree | 279fd6df2ad43db4bd6afb0e4c783f3596c00cad /src/soc/intel/skylake/chip.h | |
| parent | c787a246f963621f1b48577881ac86fe5a3c15c7 (diff) | |
| download | coreboot-9c1c00968c943659bab2a817892e5a9be9dfb7c0.tar.gz coreboot-9c1c00968c943659bab2a817892e5a9be9dfb7c0.tar.bz2 coreboot-9c1c00968c943659bab2a817892e5a9be9dfb7c0.zip | |
soc/intel/skylake: Enable thermal subsystem depending on devicetree
Currently SA thermal subsystem gets enabled by the option Device4Enable,
but this duplicates the devicetree on/off options. Therefore depend on
the devicetree for enablement of the SA thermal subsystem controller.
All corresponding mainboards were checked if the devicetree
configuration matches the Device4Enable setting, and missing entries
were added.
Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index fc86cfd58f8f..e332a6bb8ee8 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -336,7 +336,6 @@ struct soc_intel_skylake_config { u32 LogoPtr; u32 LogoSize; u32 GraphicsConfigPtr; - u8 Device4Enable; u8 RtcLock; /* GPIO IRQ Route The valid values is 14 or 15*/ u8 GpioIrqSelect; |