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| author | Felix Singer <felixsinger@posteo.net> | 2020-12-06 11:51:10 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-08 20:50:27 +0000 |
| commit | d60abfcb74ab4580f95cba1f8bfd71824acd7de6 (patch) | |
| tree | b884cf2c9a923c2fc977721b3af85aef58befeb2 /src/soc/intel/skylake/chip.h | |
| parent | bd7020d68cca2d64869e9fd59cfcb125d80589ad (diff) | |
| download | coreboot-d60abfcb74ab4580f95cba1f8bfd71824acd7de6.tar.gz coreboot-d60abfcb74ab4580f95cba1f8bfd71824acd7de6.tar.bz2 coreboot-d60abfcb74ab4580f95cba1f8bfd71824acd7de6.zip | |
soc/intel/skylake: Shorten SATA mode enum value names
The Skylake FSP isn't used by coreboot anymore. Therefore, drop the
misleading comment and the "KBLFSP" extension from the names of these
enums.
Also, drop the "MODE" extension to make their names shorter in general,
since it doesn't add any more value.
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: If37d40e4e1dfd11e9315039acde7cafee0ac60f0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48377
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/chip.h')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 0bab45ab22c9..58d172f074f4 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -142,11 +142,8 @@ struct soc_intel_skylake_config { /* SATA related */ enum { - /* Documentation and header files of Skylake FSP disagree on - the values, Kaby Lake FSP (KabylakeFsp0001 on github) uses - these: */ - KBLFSP_SATA_MODE_AHCI = 0, - KBLFSP_SATA_MODE_RAID = 1, + SATA_AHCI = 0, + SATA_RAID = 1, } SataMode; u8 SataSalpSupport; u8 SataPortsEnable[8]; |