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| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-06-18 15:56:11 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-28 21:47:52 +0000 |
| commit | 360684b41aec795d254dcaac1cefb4acf9e129d3 (patch) | |
| tree | c5bbde89d9734c08e7fea993e0403ee05f570091 /src/soc/intel/skylake/cpu.c | |
| parent | 5270ce133e068fd35a985b62a22ca64ca2fa9696 (diff) | |
| download | coreboot-360684b41aec795d254dcaac1cefb4acf9e129d3.tar.gz coreboot-360684b41aec795d254dcaac1cefb4acf9e129d3.tar.bz2 coreboot-360684b41aec795d254dcaac1cefb4acf9e129d3.zip | |
soc/intel/common: add TCC activation functionality
This enables to configure the Thermal Control Circuit (TCC) activation
value to new value as tcc_offset in degree Celcius. It prevents any
abrupt thermal shutdown while running heavy workload. This helps to
take early thermal throttling action before CPU temperature reaches
maximum operating temperature TjMax value. Also, cleanup local functions
from previous intel soc specific code base like for apollolake, broadwell,
skylake and cannonlake.
BUG=None
BRANCH=None
TEST=Built for volteer platform and verified the MSR value.
Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/cpu.c')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 22 |
1 files changed, 1 insertions, 21 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index a5454355996f..d941df70b27d 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -27,26 +27,6 @@ #include "chip.h" -static void configure_thermal_target(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - - /* Set TCC activation offset if supported */ - msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { - msr = rdmsr(MSR_TEMPERATURE_TARGET); - msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (conf->tcc_offset & 0xf) << 24; - wrmsr(MSR_TEMPERATURE_TARGET, msr); - } - msr = rdmsr(MSR_TEMPERATURE_TARGET); - msr.lo &= ~0x7f; /* Bits 6:0 */ - msr.lo |= 0xe6; /* setting 100ms thermal time window */ - wrmsr(MSR_TEMPERATURE_TARGET, msr); -} - static void configure_isst(void) { config_t *conf = config_of_soc(); @@ -333,7 +313,7 @@ void soc_init_cpus(struct bus *cpu_bus) printk(BIOS_ERR, "MP initialization failure.\n"); /* Thermal throttle activation offset */ - configure_thermal_target(); + configure_tcc_thermal_target(); } int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) |