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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-22 23:05:06 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-04 19:25:02 +0000 |
| commit | 7736bfc443a913a9cde46406bcfc38015ec71f47 (patch) | |
| tree | 5b107551301bbaadc538b0c2ac7c52125462beb3 /src/soc/intel/skylake/cpu.c | |
| parent | e75a64f822931a5fbdd80f20c4d168a5c346e01a (diff) | |
| download | coreboot-7736bfc443a913a9cde46406bcfc38015ec71f47.tar.gz coreboot-7736bfc443a913a9cde46406bcfc38015ec71f47.tar.bz2 coreboot-7736bfc443a913a9cde46406bcfc38015ec71f47.zip | |
soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig
The devicetree is not made for user-choosable options, thus introduce
Kconfig options for both SGX and the corresponding PRMRR size.
The PRMRR size Kconfig has been implemented as a maximum value. At
runtime the final PRMRR size gets selected by checking the supported
values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest
to the chosen one.
When "Maximum" is chosen, the highest possibly value from the MSR gets
used. When a too strict limit is set, coreboot will die, printing an
error message.
Tested successfully on X11SSM-F
Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/skylake/cpu.c')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index bfed528a0693..080dba0b13b4 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -442,8 +442,6 @@ static void cpu_lock_aesni(void) /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { - config_t *conf = config_of_soc(); - /* Clear out pending MCEs */ /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears @@ -479,7 +477,7 @@ void soc_core_init(struct device *cpu) enable_turbo(); /* Configure Core PRMRR for SGX. */ - if (conf->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) prmrr_core_configure(); } @@ -502,7 +500,6 @@ static void fc_lock_configure(void *unused) static void post_mp_init(void) { int ret = 0; - config_t *conf = config_of_soc(); /* Set Max Ratio */ cpu_set_max_ratio(); @@ -519,7 +516,7 @@ static void post_mp_init(void) ret |= mp_run_on_all_cpus(vmx_configure, NULL); - if (conf->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) ret |= mp_run_on_all_cpus(sgx_configure, NULL); ret |= mp_run_on_all_cpus(fc_lock_configure, NULL); |