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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-09-22 21:56:17 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-02 13:09:42 +0000 |
| commit | 48fb573e1ffffa44e79bebb9095be17f2242413d (patch) | |
| tree | 9d490ab918b799719c5c016ab4a772a3a7d15a98 /src/soc/intel/skylake/finalize.c | |
| parent | 7253e7a135b6b40218cb714aa9207a579de1364c (diff) | |
| download | coreboot-48fb573e1ffffa44e79bebb9095be17f2242413d.tar.gz coreboot-48fb573e1ffffa44e79bebb9095be17f2242413d.tar.bz2 coreboot-48fb573e1ffffa44e79bebb9095be17f2242413d.zip | |
soc/intel/skylake: set LT_LOCK_MEMORY at end of POST
Use the new common function to set LT_LOCK_MEMORY at end of POST to
protect SMM in accordance to Intel BWG.
Tested successfully on X11SSH-M by disabling SGX and running chipsec.
Change-Id: I623e20a34667e4df313aeab49bb57907ec75f8a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/skylake/finalize.c')
| -rw-r--r-- | src/soc/intel/skylake/finalize.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 4cc9c8362b75..58a87012d77c 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -20,6 +20,7 @@ #include <bootstate.h> #include <console/console.h> #include <console/post_codes.h> +#include <cpu/x86/mp.h> #include <cpu/x86/smm.h> #include <device/pci.h> #include <intelblocks/cpulib.h> @@ -123,6 +124,9 @@ static void soc_lockdown(struct device *dev) reg8 |= SMI_LOCK; pci_write_config8(dev, GEN_PMCON_A, reg8); } + + /* Lock chipset memory registers to protect SMM */ + mp_run_on_all_cpus(cpu_lt_lock_memory, NULL); } static void soc_finalize(void *unused) |