summaryrefslogtreecommitdiffstats
path: root/src/soc/intel/skylake/gpio.c
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2015-08-07 22:57:42 -0500
committerAaron Durbin <adurbin@chromium.org>2015-08-14 15:20:46 +0200
commitf50b25d7e2c979e2b8cddb76039afcdeb686e1c0 (patch)
treebff6948ef7335999a139fadf5b682f66ca4a4333 /src/soc/intel/skylake/gpio.c
parent9a8dc37cdd9486926c6b5416dd48f4f075b2612d (diff)
downloadcoreboot-f50b25d7e2c979e2b8cddb76039afcdeb686e1c0.tar.gz
coreboot-f50b25d7e2c979e2b8cddb76039afcdeb686e1c0.tar.bz2
coreboot-f50b25d7e2c979e2b8cddb76039afcdeb686e1c0.zip
skylake: remove ec_smi_gpio and alt_gp_smi_en
The ec_smi_gpio and alt_gp_smi_en devicetree options are goign to be removed. The plan for skylake is to set the settings by the mainboard through either gpio pad configuration or through helper functions. Moreover, these values only allow *1* SMI GPIO configuration in that the following has to be true: alt_gp_smi_en = 1 << (ec_smi_gpio % 24) If not, then another gpio(s) from the same group has the SMI_EN bit set for it. Lastly, remove all the subsequent dependencies as they are no longer used: enable_alt_smi() and gpio_enable_group(). BUG=chrome-os-partner:43778 BRANCH=None TEST=None Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291931 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/gpio.c')
-rw-r--r--src/soc/intel/skylake/gpio.c18
1 files changed, 0 insertions, 18 deletions
diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 18638873f7b5..afd838f105d5 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -371,21 +371,3 @@ void gpio_enable_all_smi(void)
0xFFFFFFFF);
}
}
-
-void gpio_enable_groupsmi(gpio_t gpio_num, u32 mask)
-{
- u32 gpioindex = 0;
- u32 smien = 0;
-
- if (gpio_num > MAX_GPIO_NUMBER)
- return;
-
- gpioindex = (gpio_num / MAX_GPIO_PIN_PER_GROUP);
-
- pcr_read32(gpio_group_info[gpioindex].community,
- gpio_group_info[gpioindex].smienoffset, &smien);
- smien |= mask;
- /* Set all GPI SMI Enable bits by writing '1' */
- pcr_write32(gpio_group_info[gpioindex].community,
- gpio_group_info[gpioindex].smienoffset, smien);
-}