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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-05-12 18:23:27 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-07-16 17:24:48 +0200 |
| commit | 1d14b3e926c15027f9272f1e80b8913fef8cf25d (patch) | |
| tree | b3d89ad4bb1b0ea5ac05d1d7dc6cbf26ec93e6c3 /src/soc/intel/skylake/include/soc/device_nvs.h | |
| parent | b000513741d330947bb832a5835378e35bdfb394 (diff) | |
| download | coreboot-1d14b3e926c15027f9272f1e80b8913fef8cf25d.tar.gz coreboot-1d14b3e926c15027f9272f1e80b8913fef8cf25d.tar.bz2 coreboot-1d14b3e926c15027f9272f1e80b8913fef8cf25d.zip | |
soc/intel: Add Skylake SOC support
Add the files to support the Skylake SOC.
Matches chromium tree at 927026db
BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform
Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include/soc/device_nvs.h')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/device_nvs.h | 33 |
1 files changed, 18 insertions, 15 deletions
diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h index 7dab40da6acb..822c976a1562 100644 --- a/src/soc/intel/skylake/include/soc/device_nvs.h +++ b/src/soc/intel/skylake/include/soc/device_nvs.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,31 +15,33 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ -#ifndef _BROADWELL_DEVICE_NVS_H_ -#define _BROADWELL_DEVICE_NVS_H_ +#ifndef _SOC_DEVICE_NVS_H_ +#define _SOC_DEVICE_NVS_H_ #include <stdint.h> /* Offset in Global NVS where this structure lives */ #define DEVICE_NVS_OFFSET 0x1000 -#define SIO_NVS_DMA 0 -#define SIO_NVS_I2C0 1 -#define SIO_NVS_I2C1 2 -#define SIO_NVS_SPI0 3 -#define SIO_NVS_SPI1 4 -#define SIO_NVS_UART0 5 -#define SIO_NVS_UART1 6 -#define SIO_NVS_SDIO 7 -#define SIO_NVS_ADSP 8 +#define SIO_NVS_I2C0 0 +#define SIO_NVS_I2C1 1 +#define SIO_NVS_I2C2 2 +#define SIO_NVS_I2C3 3 +#define SIO_NVS_I2C4 4 +#define SIO_NVS_I2C5 5 +#define SIO_NVS_SPI0 6 +#define SIO_NVS_SPI1 7 +#define SIO_NVS_UART0 8 +#define SIO_NVS_UART1 9 +#define SIO_NVS_UART2 10 typedef struct { - u8 enable[9]; - u32 bar0[9]; - u32 bar1[9]; + u8 enable[11]; + u32 bar0[11]; + u32 bar1[11]; } __attribute__((packed)) device_nvs_t; #endif |