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| author | Subrata Banik <subrata.banik@intel.com> | 2016-11-23 00:54:47 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-30 16:54:36 +0100 |
| commit | 0068dfdcc8c2a80508cdd44909d9a2561a30a0e5 (patch) | |
| tree | 5ddb85a539c8d65c3535879b19dc7133c054a4ff /src/soc/intel/skylake/include/soc/gpio.h | |
| parent | eedf6d8aa81e85b52d3c150dc992cbfb3077988d (diff) | |
| download | coreboot-0068dfdcc8c2a80508cdd44909d9a2561a30a0e5.tar.gz coreboot-0068dfdcc8c2a80508cdd44909d9a2561a30a0e5.tar.bz2 coreboot-0068dfdcc8c2a80508cdd44909d9a2561a30a0e5.zip | |
soc/intel/skylake: Remove pad configuration size hardcoding
Existing GPIO driver inside coreboot use some hardcoded magic number
to calculate gpio pad offset. Avoid this kind of hardcoding.
Change-Id: I6110435574b141c57f366ccb1fbe9bf49d4dd70a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17571
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include/soc/gpio.h')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/gpio.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index dd9b9a340c25..75d8abe63a69 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -19,6 +19,8 @@ #include <soc/gpio_defs.h> +#define GPIO_DWx_SIZE(x) (sizeof(uint32_t) * (x)) + #define CROS_GPIO_DEVICE_NAME "INT344B:00" #ifndef __ACPI__ |