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| author | Duncan Laurie <dlaurie@chromium.org> | 2015-12-10 01:00:54 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-18 12:08:47 +0100 |
| commit | 63f8c0af4ba934f0a9eaefaed6ae411404962196 (patch) | |
| tree | 38c74ae378ec09d2350f167635c409b971b71b64 /src/soc/intel/skylake/include/soc/pm.h | |
| parent | 970132f7255681fd439338f0a8701573d318fa5e (diff) | |
| download | coreboot-63f8c0af4ba934f0a9eaefaed6ae411404962196.tar.gz coreboot-63f8c0af4ba934f0a9eaefaed6ae411404962196.tar.bz2 coreboot-63f8c0af4ba934f0a9eaefaed6ae411404962196.zip | |
intel/skylake: Add elog event for THERMTRIP
The THERMTRIP status bit is in GBLRST_CAUSE instead of
GEN_PMCON like the EDSv1 indicates. Read this status bit
and add an elog event if THERMTRIP has fired.
BUG=chrome-os-partner:48438
BRANCH=none
TEST=tested on chell EVT after thermtrip fired
Change-Id: Icd52b753c7f3ab0d48095279f1255dd2dd08fd59
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b090c7897a8f99a685f523990235d83fafa063b2
Original-Change-Id: I5a287d7fdae2ba8ae8585cb9a4d4dd873393e1e6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317242
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12980
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include/soc/pm.h')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pm.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index e85f1b20a0e7..79861e919f75 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -135,6 +135,8 @@ #define SWGPE_EN (1 << 2) #define HOT_PLUG_EN (1 << 1) +#define GBLRST_CAUSE0_THERMTRIP (1 << 5) + #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 |