soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC

Use the Broadwell implementation as the comparison base for Skylake.

BRANCH=none
BUG=None
TEST=None

Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10340
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

1 files changed, 38 insertions, 0 deletions

diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h
new file mode 100644
index 000000000000..9242aa9ea368
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/ramstage.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_RAMSTAGE_H_
+#define _BROADWELL_RAMSTAGE_H_
+
+#include <device/device.h>
+#include <soc/intel/broadwell/chip.h>
+
+void broadwell_init_pre_device(void *chip_info);
+void broadwell_init_cpus(device_t dev);
+void broadwell_pch_enable_dev(device_t dev);
+
+#if CONFIG_HAVE_REFCODE_BLOB
+void broadwell_run_reference_code(void);
+#else
+static inline void broadwell_run_reference_code(void) { }
+#endif
+
+extern struct pci_operations broadwell_pci_ops;
+
+#endif