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| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-06-06 14:29:53 +0530 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-07-01 08:49:11 +0000 |
| commit | a1de1a0810892c3c3a22ed6e2868fbef3bde8134 (patch) | |
| tree | 3a1a3b0b9add420797d1b6ed149718ecc5653ae3 /src/soc/intel/skylake/include | |
| parent | 9692f31a4f63f5f558466b1e88f3557259e703dd (diff) | |
| download | coreboot-a1de1a0810892c3c3a22ed6e2868fbef3bde8134.tar.gz coreboot-a1de1a0810892c3c3a22ed6e2868fbef3bde8134.tar.bz2 coreboot-a1de1a0810892c3c3a22ed6e2868fbef3bde8134.zip | |
soc/intel/skylake: Remove unnecessary P-State and Flex Ratio assignment
This patch basically does two things -
1) Remove unnecessary setting of flex_ratio to TDP nominal:
Factory configured (default) Max Non-TURBO ratio(P1) is already cofigured
in MSR_PLATFORM_INFO(0xCE).
If this Maximum Non-TURBO Ratio(P1) needs to be modified, it should be done
using MSR_FLEX_RATIO (0x194).
Here, in this code, the FLEX_RATIO is being modified by the TDP Nominal
Ratio, reading the MSR_CONFIG_TDP_NOMINAL(0x648). But this value is
actually less than the factory configured Maximum Non TURBO Ratio (P1).
So, this code is actually not required.
Also, the Bit 12 in PCH Soft Strap Register is already set in descriptor.
This Bit implies Processor Boot Max Frequency -
0 = Disable Boot Max Frequency
1 = Enable Boot Max Frequency (Default)
This setting determines if the processor will operate at maximum frequency
at power-on and boot.
Thus this patch will avoid one extra platform warm reset now onwards.
2) Remove wrongly setting Max Frequency in Bootblock phase:
In the function set_max_frequency(), the P-State max ratio was set to
TDP Nominal ratio if C-TDP was enabled, else it was set to Max Non
Trbo ratio.
But, when the cpu gets reset, it will operate with the Max-Non Turbo
ratio only, which is greater than the TDP Nominal ratio.
So, no need to set back the ratio to TDP Nominal which is lower than
the currently operating frequency.
BUG=none
BRANCH=none
TEST=Build and boot poppy
Change-Id: I24bfc86ddf0f038d85da938e41e950382fe2a6c3
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/bootblock.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 10c8de124134..62dd234db411 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -35,6 +35,5 @@ void pch_early_init(void); void pch_early_iorange_init(void); void report_platform_info(void); void report_memory_config(void); -void set_max_freq(void); #endif |