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| author | Subrata Banik <subrata.banik@intel.com> | 2016-01-19 19:19:15 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-29 16:56:01 +0100 |
| commit | fbdc71941454cd4f6dbaebb3e38d27d11ab256ea (patch) | |
| tree | d3a29b03bdd169afffbf00fa67ba09c5d9c3f30c /src/soc/intel/skylake/romstage/romstage.c | |
| parent | dcc3ecc940e95cb6a97dbea203d3680f67910b59 (diff) | |
| download | coreboot-fbdc71941454cd4f6dbaebb3e38d27d11ab256ea.tar.gz coreboot-fbdc71941454cd4f6dbaebb3e38d27d11ab256ea.tar.bz2 coreboot-fbdc71941454cd4f6dbaebb3e38d27d11ab256ea.zip | |
intel/skylake: Implement native Cache-as-RAM (CAR)
Now coreboot should do BIOS CAR setup along with NEM
mode setup.
This patch also provides a mechanism to use 16MB code caching
benefit although LLC still limited to 1M/1.5M based
on SOC LLC limit.
Here with unlimited cache line gets replaced. Now we could use
unlimited cache size along with well defined data size
[pg: updated to current upstream #defines]
BUG=chrome-os-partner:48412
BRANCH=glados
TEST=Builds and Boots on FAB4 SKU2/3.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: pchandri <preetham.chandrian@intel.com>
Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com>
Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b
Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a
Original-Reviewed-on: https://chromium-review.googlesource.com/320855
Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com>
Original-Tested-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13138
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index b872d39fc284..9b95f721cab1 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -96,6 +96,10 @@ void soc_memory_init_params(struct romstage_params *params, upd->SaGv = config->SaGv; upd->RMT = config->Rmt; upd->DdrFreqLimit = config->DdrFreqLimit; + if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) { + upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; + upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE_TOTAL; + } } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, @@ -232,6 +236,10 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, new->ApertureSize); fsp_display_upd_value("SaGv", 1, old->SaGv, new->SaGv); fsp_display_upd_value("RMT", 1, old->RMT, new->RMT); + fsp_display_upd_value("FspCarBase", 1, old->FspCarBase, + new->FspCarBase); + fsp_display_upd_value("FspCarSize", 1, old->FspCarSize, + new->FspCarSize); } /* SOC initialization after RAM is enabled. */ |